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Photonic silicon devices are key enabling technologies for next generation High Performance Computers. In this paper, we report the possibility to stack and optically interconnect SOI based photonic chips for future System-In-Package photonic architecture. Combining vertical grating couplers and state-of-the-art flip-chip technology, we demonstrated low loss penalties and wide spectral range optical interconnections between stacked photonic chips.
©2012 Optical Society of America
1. Introduction
The continuously increasing demand for calculation capacity, particularly needed for High Power Computers (HPC), leads to huge efforts in term of Research and Technological Development in order to increase the available data rate in this kind of systems, while controlling the power consumption of such systems. Several works on this topic have shown that a shift to optical interconnections based technologies is unavoidable to increase bandwidth between racks, boards, or processors located on the same motherboard, and even at the intra-chip level. For the latter application, the validity of the technology called “Silicon Photonics” [1] has been demonstrated by achieving optical communications between an integrated laser emitter (using die to wafer technology approach) and an integrated photodiode, through silicon waveguides, on a single SOI chip [2]. In the near future, this kind of photonic chips could also embed electronics using CMOS technology in order to integrate logic functions, amplifying stages or signal processing functions [3], leading to a full opto-electronic System On Chip (SoC).
However,, the SoC approach is not the only way to build dense multifunctional devices. For example, memory devices currently use a chip stacking approach to increase the circuit density of a single package. In future applications, when optics are used at the chip level, some optical links would have to be designed between independent chips. For example stacked photonic chips would use silicon optical waveguides to communicate. These kind of interconnections are called Optical Proximity Communications (OPxC) [4-5], and can be formally considered as a System-In-Package approach.
The challenge to achieve such optical interconnections is obviously the mechanical alignment accuracy required between the stacked chips, in order to obtain a proper alignment between the optical beams. Typically this accuracy should be on the order of the micrometer.
In this paper, we suggest to take advantage of the self-alignment properties of the Indium solder bumps to get suitable alignment between the chips. This technology also achieves simultaneously multiple and dense electrical interconnections. It has been developed at CEA-LETI and applied to various opto-electronic devices such as Infrared CCD arrays [6], or datacom optical links where it was used for the self-alignment of a singlemode optical fiber in front of a VCSEL [7]. The goal of this study is to combine the Indium bump technology with optical coupling structures called Grating Couplers (GC). Grating Couplers are processed at the surface of the photonic chips and with adequate design, achieve simultaneously the extraction of the optical mode from the silicon waveguides and the redirection of the beam quasi perpendicularly to the chip surface. In addition they achieve mode conversion and enlargement of the mode size, which decreases the optical coupling tolerance and improves the mode matching with other optical elements such as a single mode optical fiber. The Test Vehicles used in the frame of this study are depicted Fig. 1 .
They are made up of a “carrier” chip and a “bridge” chip assembled together, and both include optical waveguides on SOI. Chip-to-chip optical interconnections are achieved using GC, as shown Fig. 1.
In the first part of this paper, the self-alignment properties of indium bumps are assessed. Then the design and the manufacturing process of Grating Couplers are described and coupling results between a GC and a Singlemode Fiber (SMF) are given. In a third part, the design and manufacturing process of the photonic chips used as test vehicles are presented in details. In a last section, experimental results of the optical coupling between chips are reported and discussed, with a strong focus on the measured influence of mechanical misalignment and wavelength dispersion on the optical coupling.
2. Indium bumps flip-chip alignment
The Indium bump flip-chip assembly process has originally been developed at CEA-LETI to assemble Infra red Focal Plane Arrays (IRFPA) onto CMOS readout circuits. It combines a post process onto the CMOS as well as a flip chip assembly of the chip over its circuit. The manufacturing process is achieved at LETI on a 200mm silicon production line, and is well described in [8]. It consists on creating Indium bumps over metallic pads. First, some metallic structures, called Under Bump Metallization (UBM), are deposited and etched at the future bumps location . The top layer of these structures, is formed with gold as it is a very good wetting surface for Indium, which is crucial for bump formation after deposition. Then Indium is deposited on the full wafer using vapor deposition combined with a photolithographic and lift-off process, as described Fig. 2 (top).
After the lift-off step, Indium pads with a well controlled volume are obtained on top of the UBMs. Following these fabrication steps, the reflow process is achieved to form smooth uniform bumps. It consists on heating the wafers on a chuck, slightly above the In liquidus temperature (156°C) which forces Indium to reflow and to wet on the UBM pads.
The next step is the flip-chip assembly of the top and bottom chips. It requires a conventional but high accuracy flip-chip equipment (in our case, a FC150 from Replisaurus/SET) which has an initial pre-alignment accuracy of ±5µm, compatible with the typical bump pitch (15 to 50µm) used here. This accuracy is obtained using alignment patterns like crosses that are processed at the UBM level. When a mechanical contact is detected between the two chips, the chips are heated, Indium melts again and a connection is achieved during the cooling phase. Self-alignment occurs during this step, due to centering forces [9], as illustrated Fig. 2 (bottom). CEA-LETI has done lots of work to optimize both the fabrication steps and the assembly process, it is therefore a leader in this field and achieves very low pitch (15µm) with high accuracy self-alignment (<1µm).
For opto-electronic applications some additional studies were achieved to estimate the residual misalignment using Vernier scale processed at the UBM level, as suggested by Tsunetsugu et al. [10]. For these studies the top chip was made of a glass substrate, so that a direct reading of the misalignment was possible, with a repeatability calculated to be +/− 0.1µm. Several configurations were processed with various bump diameters and filling factor. This last parameter being the ratio between the UBM total area and the chip area. We used ratios from 2 to 6%, and 10 samples per configuration.
Figure 3 demonstrates the influence of the filling factor over the residual misalignment. It also shows that with a filling factor of 6%, the residual misalignment is kept below 0.1µm for bumps diameter 25µm and 40µm. As explained in the next section, this value is suitable to get an acceptable alignment of the optical beams emitted from the Grating Couplers.
3. Grating Coupler design
The optical coupling between the device and the optical fibers is performed using grating couplers structures. The same structures have also been implemented for optical coupling between the stacked “carrier” and “bridge” chips. Grating couplers are well suited for 3D chip-to-chip optical interconnection as they lead to a vertical or quasi-vertical coupling angle with respect to the chip surface. Moreover, they can be located anywhere on the chip. In this experiment we have used well known one dimensional grating [11].
Grating couplers are diffractive structures that are placed at the end of a lateral adiabatic taper. They produce an output mode which may have the same dimensions as a standard single mode fiber, whose Mode Field Diameter is typically 10µm at 1550nm, making possible a direct butt-coupling between the fiber and the chip. The grating couplers are made on a silicon-on-insulator (SOI) substrate. The silicon structure is sandwiched between a thick SiO2 buried oxide (BOX) layer and a thinner SiO2 CVD cladding (Fig. 4 ). At the grating level, the silicon layer is partially etched by a reactive ion etching process after a DUV optical lithography.
Fig. 4 Grating coupler layers with the guided mode profile and the outcoupled beam from the waveguide towards the fiber through the grating.
If we focus on a one dimensional grating, some parameters can be given analytically according to the following formula. First, the grating period is optimum for the TE mode coupling at a given wavelength λ and a coupling angle θ with respect to the vertical, according to the phase matching condition,
where k=2π/λ is the modulus of the out-coupled wave vector, p is the diffraction order, Λ is the grating period, β=(2π/λ)neff is the real part of the propagation constant and neff is the mean effective index along one grating period. The grating used here is based on a 220nm thick silicon core sandwiched between silica layers, the grating period is Λ=632nm and the partial etching depth is 70nm: the optimum angle at 1550nm is then 14° in the air and 2D FDTD modeling gives 3dB fibre coupling loss. As the optimal coupling angle varies with respect to the wavelength, at a given coupling angle the spectral bandwidth is in the range of 30nm at 1dB below the optimum, and 60nm at 3dB.Experimentally, from our experimental batch, the grating exhibits higher fibre coupling losses, close to 6dB (Fig. 5 ). This is due to the fact that we had to use 248nm DUV optical lithography instead of 193nm: the grating features which are 316nm width are then not very well defined. This 6dB version of the GC has been implemented in the test vehicles described in section 4. However, we have already demonstrated how to reach experimentally fibre coupling losses lower than 2dB [12].
Fig. 5 Measured fibre-to-waveguide grating coupler loss at 14° coupling angle with respect to the wavelength.
Considering chip-to-chip optical coupling performed by two face–to-face grating couplers, the coupling loss is expected to be about twice the range of the fibre-to-waveguide grating coupler loss. However the coupling loss is lower, as the mode matching between two identical grating couplers is better than between a grating and an optical fibre. Indeed, the mode matching loss between a fibre and a grating is in the range of 2-3dB [13]. We can suppose the mode matching loss to be null between two gratings. Another advantage of this grating-to-grating coupling is a larger spectral bandwidth. Indeed, the spectral bandwidth of a fibre-to-waveguide grating coupler is mainly defined by the fact that the fibre is placed at a given angle above the grating coupler whose optimal coupling angle varies according to the wavelength is the range of −6° by 50nm wavelength shift. Between two identical gratings, we have also a self coupling angle matching as the optimal coupling angles of the two gratings vary the same way according to the wavelength.
4. Stacked chips manufacturing process and assembly of photonic chips
We designed and processed photonic chips including silicon waveguides and Grating Couplers intended to be flip-chipped using the Indium bumps technology. We used 200 mm SOI wafers with 2µm thick buried oxide and optical waveguides of cross-section 220x500 nm. Grating Coupler designs have already been described in section 3. We designed two types of structures, corresponding to “carrier chips” and “bridge chips”. These two structures are processed on the same wafer, followed by the post process achieving the UBM and Indium bumps (note that Indium bumps are located on the “carrier” chips). After dicing, the “bridge” chip is flip-chipped onto the “carrier” chip as shown on Fig. 6 ; and the residual gap between both chips due to the bump height has been filled with an optically clear underfill of refractive index 1.5. Dimensions of carrier and bridge chips are 7.2x5.5mm and 7.2x2.5 mm respectively. We designed two kinds of light paths in order to evaluate the optical characteristics of the waveguides, grating couplers and assembly. These light paths are depicted Fig. 7 .
Fig. 6 Sketch of Carrier and Bridge chips before flip-chip assembly, showing reference and test paths.
Fig. 7 Photograph of an actual device showing the Indium bumps and the top and bottom GCs. The red arrowed lines describe light path.
Reference paths are direct circuits through the “carrier” chip with input and output fiber grating couplers at each side. Light is launched or collected from standard, flat cleaved singlemode fibers that are positioned in front of the input and output GC using micrometric actuators. The measured fiber-to-fiber transmission through the reference paths gives the reference loss values with respect to the wavelength. This reference loss includes both waveguide propagation losses and fiber grating coupler losses.
Test paths are characterized once the bridge chip is assembled. Light is launched at the input port of the carrier chip, then travels to a first Grating Coupler that decouples and redirects light to the bridge chip. A corresponding GC, designed on the bridge chip recouples the light into the bridge chip waveguide. Flip-chip assembly enables accurate relative positioning of these two Grating Couplers. Light is then transmitted through the bridge waveguide to a second pair of GCs, and then recoupled to the carrier chip. It is then collected into the output fiber. Thus the total insertion loss of the test path is measured. The loss contribution of the Grating Coupler Interconnections is obtained by deducting the reference loss from the test path loss.
We have designed structures with two and four chip-to-chip vertical optical interconnections on the same bridge chip, denoted TEST_2 and TEST_4 on Fig. 6. This structure can be considered as an optical “daisy chain”, allowing the measurement of averaged grating to grating optical losses. Figure 7 illustrates the optical path through “carrier” and “bridge” chips.
We also have implemented configurations with an arbitrary offset between the bridge and the carrier grating coupler in order to observe the influence of the relative positioning of the Grating Coupler on the measured coupling losses.
5. Test and self-alignment characterization
As expected, we have measured transmission losses through the grating-to-grating interconnection that exhibits a wider spectral range than the fiber to grating interconnection. Figure 8 shows the transmission spectral curve of such a connection.
Fig. 8 Tested device (left) and Coupling loss of the grating-to-grating interconnection over the 1500-1600 nm spectral range (right).
The absolute insertion loss is rather flat, from −8 to −6 dBm, on the 1500 to 1580 nm spectral range, allowing also wavelength multiplexed signals to be transmitted between the two chips. This transmission loss level is close to the expected losses according to the manufacturing technology used. As no additional loss is observed, micrometric residual shift is achieved with the self-alignment method.. This is consistent with the expected measurement done using vernier scales on transparent chips (refer to section 2), however it is difficult to conclude on the absolute value of the residual misalignment.
We also derived a curve illustrating the dependency of transmission loss versus misalignment, using the offset configuration described earlier. The optimal offset δ of the optical axis above a grating coupler is δ=4µm. Therefore, the optimal offset between two grating couplers is δ=8µm. However, due to the gap between the gratings, the optimal offset becomes δ=8+h.tan(θ) with h the optical gap between the gratings and θ the optimal grating coupling angle at the central wavelength, as illustrated Fig. 9 .
For our application h is between 30 and 35µm and θ between 9 and 11° which leads to an optimal offset δ between 13−15µm. This estimation is validated by experimental measurements (Fig. 10 ). Moreover, the offset sensitivity is 1dB at 3µm which also fits the theory as the grating couplers exhibit 10µm mode field diameter. The maximum coupling loss is obtained for a relative offset value of 16 µm, confirming that the residual misalignment is kept below 2 µm from target.
4. Conclusion and outlook
We successfully demonstrated the validity of Indium bumps based flip-chip technology in order to achieve Optical Proximity Communication between stacked SOI photonic chips, achieving sub micrometric alignment between grating coupler structures. This technique can be applied to Photonic System-In-Package architectures using photonic silicon interposers.
Moreover, tolerances of ±5µm which were proven to keep alignment penalty as low as 3 dB are compliant with next generation high throughput flip-chip equipment that will be used for 3D microelectronic interconnections.
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