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Abstract
Silicon nitride (SiN) waveguides need to be thick to show low dispersion which is desired for nonlinear applications. However, high quality thick SiN produced by chemical vapour deposition (CVD) contains high internal stress, causing it to crack. Crack-free wafers with thick SiN can be produced by adding crack barriers. We demonstrate the use of dicing trenches as a simple single-step method to produce high quality (loss<0.5 dB/cm) crack-free SiN. We show Kerr-comb generation in a ring resonator to highlight the high quality and low dispersion of the waveguides.
© 2022 Optica Publishing Group under the terms of the Optica Open Access Publishing Agreement
1. Introduction
The fabrication of low-loss ($<0.5$ $dB/cm$) low-dispersion ($|D| < 100$ $ps/(nm\: km)$) engineered waveguides in SiN requires the deposition of a thick high quality layer. Plasma enhanced CVD (PECVD) yields thick films at low temperatures, but these films show an increased absorption [1] which may be due to a high deposition rate resulting in a less "tidy" layer. LPCVD shows the lowest losses but comes with high tensile stress that causes cracks so that crack-free single deposition layers are limited to roughly 400 $nm$ [2]. Silicon rich films can be thicker but again suffer from absorption likely due to two-photon absorption in silicon clusters [3,4], so that we will focus on stoichiometric films here. The stoichiometry is mainly determined by the ratio of the flow of dichlorosilane (DCS) to ammonia (NH3) where NH$_{3}$/DCS ratios between 2 and 20 result in stoichiometric film with a Si/N ratio of 3/4 and a film stress over 1 $GPa$ [5].
The origin of the tensile stress is sometimes attributed to differences in thermal expansion between the silicon substrate and the Silicon Nitride layer. However, the thermal expansion coefficient of silicon exceeds that of silicon nitride so that this would result in compressive stress for depositions at elevated temperatures. A more convincing model that fits our results was presented by Stadtmüller [6] where a small thermal compressive stress is predicted that is dominated by a much larger tensile stress. This large tensile component is caused by the difference in density of the atoms when absorbed on the surface before they react and after their reaction to form the final layer. Furthermore, the absorption of other molecules that are involved in the reaction inhibit perfect growth resulting in elongated or stretched bonds and a layer that is reduced in density. This model predicts that deposition at higher temperature reduces the stress since it yields a little more compressive stress and a higher surface mobility during formation. It also predicts that annealing at temperatures higher than the deposition temperature means that during the annealing the thermal component also turns tensile leading to potential additional cracks. In this paper we demonstrate the use of dicing trenches as a simple single-step method to avoid cracking in high quality stoichiometric SiN.
2. Design considerations
2.1 Deposition and stress
Propagation losses in the C-band have been assigned to the first overtone of the N-H stretching vibration so that the presence of residual hydrogen has to be minimized. Annealing for an extended period (multiple hours) at 1200 $^{\circ}C$ has been shown to reduce these losses [7,8]. The layer after annealing is also more compact and has a slightly increased refractive index. The layer is also reported to have a reduced internal stress so that another layer can be deposited and thicker layers (up to 744 $nm$ without additional techniques as described below) can be achieved. This deposition-annealing-deposition method has been called "thermal cycling". Since the annealing itself comes with a risk of crack formation, a second anneal step is only done after the waveguides have been etched [7]. Further propagation losses tend to be dominated by scattering on sidewall roughness. Minimal losses (0.001 $dB/cm$) have been obtained using low (50 $nm$) waveguides that were very wide (6.5 ${\mu }m$) [9]. However, that geometry limits the dispersion to the normal dispersion regime. For most nonlinear applications the dispersion has to be small (either anomalous or normal) which requires a core thickness around 600 to 700 $nm$ [7].
For this work, an attempt was made to fabricate crack-free wafers using this ‘thermal cycling’ method. The reduction in stress was quantified by comparing two plain silicon wafers on which a single 315nm SiN layer was deposited. These wafers do not contain a thermal oxide layer and prior to deposition the native oxide is removed using 1 minute 1%HF. One wafer was annealed for 3 hours at 1150 $^{\circ}C$,reducing the layer thickness to 282nm, the other was not. The stress in the layers was found by measuring the wafer bow, before and after removing the SiN on the backside of the wafer. This measurement was performed 100 days after deposition. The stress is related to the difference in wafer bow through the Stoney equation [10]:
where $Y_s$ and $\nu _s$ are Young’s modulus and the Poisson coefficient for silicon (130 $GPa$ and 0.28 respectively [10]), $t_s$ is the substrate thickness (525 ${\mu }m$), $d_s$ is the length over which the bow is measured (here 80 $mm$), $t_f$ is the layer thickness and $\delta$ is the difference in wafer bow before and after etching the layer on the backside of the wafer.A (tensile) stress value of 1.81 $GPa$ was found for the unnannealed layer, compared to 1.56 $GPa$ for the annealed layer, confirming that annealing reduces the layer stress. However, these values are high compared to the 0.8 to 1.2 $GPa$ found in literature [1,8]. The high stress is potentially explained through the deposition recipe as described below. The recipe here has a 200 sccm flow of N2, in addition to the necessary ammonia (NH3) and dichlorosilane (DCS) flows. As discussed by Stadtmüller [6], the presence of additional gasses will lead to more intrinsic tensile stress. However, the cleanroom facility limits variation of the process parameters so that N2 could not be omitted.
Layers of 650 $nm$ and 735 $nm$ were fabricated using the thermal cycling method. Although some 650 $nm$ layers were suitable for fabrication, none of the layers were fully crack free, likely due to the high amount of stress.
2.2 Current techniques
Another strategy to reach thicknesses above 400 $nm$ include twist-and-grow where the deposition is done in multiple steps, very slowly and the wafer is cooled and rotated in between depositions. Thicknesses up to 1 micron have been reported [10] for a recipe using a very low hydrogen content. A completely different approach is taken in the "Damascene reflow" [11] and "TriPlex filled box" [12]. Here trenches are etched in a silicon oxide layer that are filled with SiN and subsequently planarized. The surrounding silicon oxide and limited lateral size of the SiN prevents cracking. Since the sidewall roughness is now determined by the etched walls in the silicon oxide, the walls can be smoothed by including a reflow before the filling generating very smooth walls and ultra-low propagation losses. The reflow however requires temperatures above 1200 $^{\circ}C$ for 18 hours. Due to limitation on oven temperature at our facility (1100 $^{\circ}C$ for 16 hours) and restrictions on the control of the hydrogen and nitrogen flow, we opted for a more traditional approach with the addition of crack barriers to prevent cracking.
2.3 Crack barriers
Luke at al. [13] reported the use of crack barriers above a thickness of 750 $nm$ based on crack behaviour reported by Nam et al. [14]. Xuan et al. [15] and Krükel et al. [4] also reported the use of barriers. All three reported that cracks always started from the edge of the wafer so that barriers can protect an enclosed area, but that a single step barriers profile (a single-level trench) does not prevent cracks from propagating. Luke et al. used a diamond pen to create scratches and it was hypothesized by Xuan et al. that the rough profile of those trenches effectively acted as multi-level (angled) profile. Furthermore, Luke only enclosed an area of 5x5cm between the scratches. Xuan et al. also reported that very deep trenches, etched 120 ${\mu }m$ into the substrate did stop cracks. However, 120 ${\mu }m$ etches require Deep Reactive Ion Etching (DRIE) with the Bosch process which requires an additional lithography and etching step (twice if performed on wafers with a thermal oxide layer). Using a dicing blade, trenches can be made reliably and deep without any lithography. We used a standard u-shaped silicon dicing blade.
Four variations of crack barriers were tried, three of which are shown in Fig. 1: 1) Barriers made by diamond pen (following Luke) to enclose a 5x5cm square area. 2) Barriers made by diamond pen only along the edge of the wafer, creating a larger useful surface. 3) Barriers of 25 ${\mu }m$ deep using a 30 ${\mu }m$ dicing blade. The trenches were applied in an octagon pattern to maximize the useful area on the wafer. 4) Barriers of 120 ${\mu }m$ deep using the same dicing blade. Five parallel trenches were used in all configurations, the trenches with the dicing blades had a 100 ${\mu }m$ pitch.
Fig. 1. The different crack barrier strategies; from left to right: diamond pen square, diamond pen circular and dicing in an octagon pattern. The dicing was done at 25 ${\mu }m$ depth and 120 ${\mu }m$ depth.
3. Fabrication
All wafers produced without crack barriers using the thermal cycling strategy showed cracks at 650 $nm$ (small normal dispersion, see Table 2 and Fig. 2) and 735 $nm$ thickness (small anomalous dispersion). Some of the 650 $nm$ wafers showed a crack-free area of more than 50% of the total area. For the wafers with crack barriers we aimed at two thicknesses: 650 $nm$ and 800 $nm$. The 650 $nm$ wafers were created using three depositions: 82.5, 307.3 and 262.8 $nm$ for a total of 652.5 $nm$. The 82.5nm was not by design but the result of an unrelated alarm followed by an emergency termination of the process. The 800 $nm$ wafers had an additional deposition of 152.5 $nm$ yielding a total thickness of 805.1 $nm$. The layers were deposited at a temperature of 750 $^{\circ}$C and a pressure of 150 mTorr with flow-rates of 25 sccm DCS, 250 sccm NH3 and 200 sccm N$_{2}$. For these parameters, the layers grow at a speed of approximately 1 $nm/min$. A maximum layer thickness of 300 nm per deposition is imposed by the process control.
Fig. 2. Left: Successful crack arrest by crack barriers applied with a diamond scribe. Right: Failed crack arrest by (shallow) diced crack barriers from shallow diced barrier
The wafers that were used for lithography contain a thermal oxide layer of 8 ${\mu }m$. The lithography started with a dehydration bake for 5 $min$ at 120 $^{\circ}$C. The wafer was primed by spinning HexaMethylDiSilazane (HMDS) for 45 seconds at 4000 rpm. 1.5 ml of a negative E-beam resist, AR-N7520.18 was spun for 180 seconds at 1500 rpm (for the 650 $nm$ layers, for 800 $nm$ layer 1000 rpm was used). The resist was pre-baked at 85 $^{\circ}$C for 1 minute. Subsequently, 1.5 ml of an anti-charging coat was spun at 2000 rpm for 45 seconds followed by another pre-bake at 50 $^{\circ}$C for 2 minutes. The waveguides were written using Electron Beam Lithography (EBL) on a RaithEBPG5150 using a dose of 800 ${\mu }C/cm^{2}$ for the 650 $nm$ resist (1000 ${\mu }C/cm^{2}$ for the 800 $nm$). The resist was developed with AR300-47 for 1 minute. The wafer was cleaned by a quick dump rinse and dried by spinning at 2500 rpm for 1 minute. After development a 3-minute reflow step at 145 $^{\circ}$C was used to decrease sidewall roughness. The E-Beam machine has maximum write fields of 500x500 ${\mu }m$ and stitching errors between write-fields can go as high as 100 $nm$. The layout and order of the writing were chosen to minimize stitching errors by fitting rings into one write-field and writing critical transitions in subsequent write fields.
The etching was done using CHF$_{3}$/O$_{2}$. We used a parallel plate Reactive Ion Etching (RIE), the Plasma-Therm 790, with an interferometer end-point detection. At a flow 25 sccm of CHF$_{3}$ and 5 sccm O$_{2}$ at a pressure of 20 mTorr and a power of 250W, SiN and SiO both etch at 32 $nm/min$ and the resist etches at 17.5 $nm/min$. The etching was continued for 30 seconds once the end-point was reached to ensure complete etching on the full wafer. Remaining resist was stripped by O$_{2}$ plasma in a PVA TePla360. To avoid polymer formation inside the chamber we etched for a maximum of 5 minutes at the time and used an oxygen plasma clean in between the etches (following [7]). Both sides of the wafer need to be etched before annealing. During the back-etch the structures on the front were protected using a 1.7 ${\mu }m$ layers of photoresist. Annealing to reduce the hydrogen content was done only after the etching. Following [16,17], the wafers were annealed at 1100 $^{\circ}$C for 20 minutes in an oxygen environment for native oxidation of the SiN surface, followed by 3 hours at 1150 $^{\circ}$C in an N$_{2}$ environment (which is the maximum temperature imposed by process control).
Finally, a cladding was deposited in two steps. First we deposited 1 ${\mu }m$ of SiO$_{2}$ by LPCVD using 40 sccm TEOS and 30 sccm N$_{2}$ at a pressure of 20 mTorr and a temperature of 730 $^{\circ}$C. LPCVD minimizes the void formation but can only be used up to 1.2 ${\mu }m$. This layer was densified using an annealing step at 1100 $^{\circ}$C for 3 hours in a nitrogen environment. We then deposited 8 ${\mu }m$ of SiO using PECVD using an Oxford Plasmalab 80 Plus (2$\%$ SiH$_{4}$ in Ar).
A scanning electron microscopy (SEM) image of a cross-section of the coupling region of a ring is shown in Fig. 3. The bus waveguides and ring waveguides have a trapezoidal shape with a sidewall angle of 81$^{\circ}$ and a top width of 1.5 ${\mu }m$. These waveguides support four TE modes (TE$_{00}$, TE$_{10}$, TE$_{01}$ and TE$_{20}$). Light is coupled mainly into the TE$_{00}$ mode of the bus waveguide. Coupling to the ring also excites higher order modes. In general the coupling to the TE$_{10}$ is the strongest.
The chips were diced and polished. The patterns that we produced include waveguides, ring resonators, Euler bends curving into the coupler regions for the ring resonators and inverted tapers to couple light onto and off the chips. Facet coupling losses using a butt-coupled fiber ranged from 7.5 to 10.2 dB. Coupling losses using a lensed fiber for the Kerr-Comb experiments ranged from 3.1 to 4 dB.
Fig. 3. SEM image of two 0.8x1.5 ${\mu }m$ waveguides (bus and ring) as produced for this work. The cross-section was made using a Focused Ion Beam (FIB).
4. Results
4.1 Crack inspection
Inspection under grazing incidence light proved the most effective method for detection of cracks. The wafers were inspected after depositions, before any etching. Table 1 show the results for layer thicknesses of 650 $nm$ and 800 $nm$. Of the wafers with the square scribed crack barriers, only two were crack free for the 650 $nm$ thickness but these remained crack-free after the layer was increased to 800 $nm$. We attribute this unexpected result to the low reproducibility of scribed lines. The first set (for 650 $nm$) was probably not made aggressively enough and thus less deep.
Table 1. Number of wafers where cracks were found within the intended crack-free area, for each method used. *=this wafer was initially found to have no cracks in the intended area, but a crack was found during inspection 75 days later. No wafer handling had occurred in this period.
Figure 2 left shows examples of a successful termination of a crack on a scribed line. The crack appears to terminate without deflection. On the right is an example of an unsuccessful crack arrest. The crack "jumps" the barrier with small deflections at the jumps. Figure 4 shows examples of successful crack arrest for the deep dicing trenches. The behaviour at the barrier is now marked different; the cracks deflect close to the barrier, run parallel to the barrier and sometimes merge with the barrier but do not cross it. From these test it is clear that deep (120 ${\mu }m$) dicing is an effective and sufficient method to create crack barriers.
Fig. 4. Effect of 120 ${\mu }m$ deep, diced crack barriers. Left: Two cracks near an intersection of crack barriers. The bottom left part of this image is the crack-free area. Right: Crack being ‘deflected’ near crack barriers. In this image the crack-free area is on the right hand side.
4.2 Dispersion and loss
The dispersion and losses were characterized by measuring the transmission of the waveguides coupled to ring resonators at $1$ pm resolution. An example of a section of such a measurement is shown in Fig. 5. The depth and width of the peaks can be used to extract the propagation loss per round trip in the resonator [18].
The peaks can further be grouped based on the spacing which reveals the different modes as well as the dispersion of these modes. To do so, we define the integrated dispersion $D_{int}$, following [1]:
Here, $\mu$ is the peak number counted from the central peak (located at angular frequency $\omega _0$). $D_1$ is the central FSR of the mode. $D_2$ and $D_3$ are the second- and third-order dispersion coefficients. Note that the group velocity dispersion is related to $D_2$ as $\beta _2 = -\frac {n_g}{c}\frac {D_2}{D_1^{2}}$ [19]. The integrated dispersion and the losses for the $TE_{00}$ mode are show in Fig. 6. Although the algorithm does not identify all the peaks, a clear grouping emerges. This particular ring supported 4 modes ($TE_{00}, TE_{10}, TE_{01}, TE_{20}$). Using simulations, the first two could be identified based on their FSR, but the simulation were not specific enough to distinguish which the latter two from each other.
Fig. 5. Transmission spectrum of a ring resonator with 150 ${\mu }m$ radius, consisting of a 0.8x1.5 ${\mu }m$ waveguide, measured for TE polarization.
Fig. 6. Left: Integrated dispersion [18] for the 150 ${\mu }m$ radius, 0.8x1.5 ${\mu }m$ waveguide, showing the deviation of each mode from an FSR of 151.93 GHz. The modes labelled ‘m2’ and ‘m3’ correspond to the TE01 and TE20 modes, but simulations were not accurate enough to identify which was the TE01 and which was the TE20 mode. The TE00 mode has a dispersion parameter of 98.7 $ps / nm\: km$ (anomalous dispersion). Right: Histogram of propagation losses found for the TE00 mode. The most likely value is ~0.35$dB/cm$.
The results for all waveguides are listed in Table 2. The dispersion matches with simulations performed with the FDE solver of Lumerical MODE solutions and shows that it is possible to engineer the dispersion close to zero using the thickness of the waveguides as the tuning parameter. It is likely that the dominant propagation loss is due to sidewall roughness as the widest waveguides, with the lowest interaction of the field with the side walls, show the lowest losses. The bending radius appears to be a minor factor for radii above $75$ ${\mu }m$.
Table 2. Modes, dispersion and losses for different waveguides. The widths given are the design widths of the waveguides (the width at the top of each waveguide). The base widths are larger, corresponding to the 81$^{\circ }$ sidewall angle. The coupling loss is the (lowest experimentally found) coupling loss per facet between the inverted taper and an PM1550-XP fiber.
4.3 Kerr comb generation
To highlight the applicability of these waveguides for nonlinear optics we launched light at 1550 $nm$ at various powers into a ring (radius of 75 ${\mu }m$) to observe Kerr frequency comb generation. Figure 7 shows the evolution of such a comb starting from on-chip powers close to the threshold (at 62 mW) to a fully developed spectrum at 248 mW.
5. Discussion and conclusion
The results in this paper demonstrate that thick SiN low loss waveguides can be reliably produced using crack barriers and standard processes. Crack-free layers of up to 800 $nm$ were fabricated using the methods described. We do not know what the limiting thickness is before cracks would appear inside the area enclosed by crack barriers. The propagation losses are dominated by scattering at sidewall roughness. Using waveguides with a larger width reduces the propagation losses, but for thick waveguides this allows for the propagation of multiple modes and the coupling between the fundamental mode of a bus waveguide and the fundamental mode of a ring will decrease. Alternatively, reducing the propagation loss can be done by reducing the sidewall roughness as described by Ji et al. [20].
We confirm that deep (120 ${\mu }m$) crack barriers provide a crack-free area, even with a single-step profile, and demonstrate a straightforward method to apply these without additional lithography and etching steps. However, we found that the behaviour of such crack barriers is different from (shallow) scribed barriers; Where the scribed barriers stop cracks, the diced deeper barriers deflect them.
Acknowledgments
We would like to thank Ivo Hegeman, Ward Hendriks and the IOS group in general for their support and guidance with the measurements of the rings.
Disclosures
The authors declare no conflicts of interest.
Data availability
Data underlying the results presented in this paper are available through the 4TU repository [21].
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