1. Introduction

Digital mask projection lithography (DMPL) [1–4] is a novel micro-nanofabrication technology that can achieve high-precision micro-nanofabrication by directly projecting patterns onto the photoresist using a computer-generated “digital mask”. The “digital mask” is realized by modulating the spatial light modulator (SLM) with a digital signal. Thus, DMPL has the advantages of low cost, high flexibility, and short production cycles compared with traditional lithography [5]. This technology has been widely used in various fields, such as microelectronics, optoelectronics, and biomedical engineering. State-of-the-art DMPLs use digital mirror devices (DMDs) based SLM as digital masks to enable resist patterns with submicron-scale features. Saha [6] et al. proposed a DMD-based femtosecond laser projection two-photon lithography (FP-TPL) technique. By utilizing the dispersion property of DMD shiny gratings, two-photon polymerization could not occur effectively in the regions outside the target plane due to the elongated pulse width, realizing high-resolution two/three-dimensional patterning exposure. Kang [3] et al. established a DMPL system based on a DMD with a pixel size of 5.4µm, an optical system of 200 × reductions and NA of 0.9, and a light source of 405 nm. The photoresist patterns with a minimum feature size of 180 nm can be produced. Liu [2] et al. used a femtosecond laser with a wavelength of 400 nm as the lighting source, non-chemical magnifying adhesive as the photoresist, and DMD as the digital mask, and established the corresponding lithography system, realizing efficient lithography from micron scale to nanoscale. In recent years, maskless optical projection lithography has made significant advancements in both spatial resolution and device applications.

To further advance the development of digital masks, researchers have investigated different modulation methods. These include utilizing DMD to generate gray light intensity through binary pulse-width modulation [7] and employing novel forms of digital masks such as liquid crystal on silicon spatial light modulator (LCOS-SLM) [8–10]. However, the DMPL system still relies on a projection optical imaging system, which imposes limitations due to the low-pass characteristics of the optical system. This gives rise to the optical proximity effect (OPE) [11,12], which is observed in state-of-the-art DMPLs [2] when manufacturing layouts with feature sizes smaller than the wavelength. Due to the influence of OPE, directly applying the target layout onto the digital mask may not yield the expected results. Moreover, digital masks suffer from the drawback of having pixel sizes typically in the micron range, which imposes limitations on the size and pitch of the fabricated pattern. This is because the pixel size of a digital mask is a fixed value, making it impossible to produce the resist pattern with a continuous line width within the same process window if the binary amplitude is employed. Additionally, the pixel period of digital masks is also fixed, preventing the production of resist patterns with continuous periods. Liu [13] proposed a method to adjust the exposure dose of DMD pixels through pulse width modulation to achieve a resist pattern that closely resembles the target pattern. However, this algorithm focuses solely on optimizing the grayscale exposure of pixels within the target layout and does not take into account pixels outside the design. Consequently, the reduction in transfer error is limited for the target design. Furthermore, this technique can only be applied to specific designs that can be directly loaded onto the digital mask. When the pitch and line width of the target layout do not align with integer multiples of the pixel period of the digital mask, it becomes unclear how to load the digital mask to achieve a resist pattern that closely matches the target layout. Therefore, there is still an urgent need in DMPL for an efficient modulation method to produce a resist pattern that accurately replicates the target layout.

In this paper, we present a novel approach called the Digital Inversion Lithography Technique (DILT) that can be utilized to optimize the modulation coefficient of the digital mask, enabling the resist pattern to match the desired target layout. It is worth noting that the target layout can be Manhattan patterns (such as integrated circuits) and non-Manhattan patterns (such as metasurfaces). DILT can reverse engineer the target layout of continuous line width and period, which breaks through the limitation of pixel size and period of digital mask. A digital mask projection lithography system is modeled whose input is the loaded modulation coefficient and whose output is the resist pattern. The difference between the output and the intended design is used as a cost function, and the modulation coefficient of the digital template is determined by finding the minimum of the cost function.

2. Methods

2.1 Digital mask projection lithography system modeling

In this paper, the “digital mask” can be achieved through binary amplitude modulation of DMD and grayscale modulation of LCOS-SLM in a coherent projection lithography system. Although DMD resembles blazed gratings [14,15], they can be approximated as amplitude-type objects because the imaging system's low pass only allows a specific diffraction order to participate in imaging. For DMD-based digital masks, each DMD pixel can only control whether the reflected light in the pixel is received by the lithography system by adjusting the angle of the digital micromirror. On the other hand, LCOS-SLM can achieve grayscale amplitude modulation by controlling the orientation direction of liquid crystal molecules within each pixel. Although the methods and principles for SLM modulation of the light field vary, the minimum range of modulation is one pixel, which is typically on the order of micrometers. The complex amplitude transmittance of the digital mask can be summarized as follows:

Figure 1(a) illustrates the diagram of the DMPL system, and the effect contrast of digital mask with optimization and non-optimization. The process begins with the illumination laser being directed onto the digital mask. The SLM on the digital mask then modulates the light field on each corresponding pixel based on the modulation coefficient we set, resulting in a digital light field. Subsequently, the optical system projects the digital light field distribution onto the image plane, where the resist pattern is located. At this stage, the photoresist interacts with the modulated light field. The photoresist molecules undergo cross-linking and become insoluble in the developer, leading to the formation of a resist pattern. This step transfers the target design from the digital mask to the resist pattern. The entire lithography system comprises two main components: the digital mask projection optical imaging model and the photoresist model. Initially, each pixel of the digital mask is sampled into points in space to facilitate further processing and calculations. A discrete representation of the digital mask's complex amplitude transmittance was then established:

 

Fig. 1. Concept and mechanism schematic of the DILT: (a) Schematic diagram of digital mask projection lithography system with optimization / non-optimization digital mask; (b) Flow chart of DILT; (c) Inverse design results (digital mask, intensity, photoresist pattern) of DILT for binary amplitude optimization and grayscale amplitude optimization.

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The photoresist model used in this research employs a constant threshold model [17]. However, the expression of the hard threshold model is not differentiable, which poses a challenge for optimization algorithms like gradient descent. To address this issue, the cost function is typically made differentiable by approximating the hard threshold function using the sigmoid function [18]. This allows for the use of gradient descent and other optimization techniques. The forward model T{}of digital mask projection lithography can be summarized as follows:

2.2 Principle of DILT

Despite the increased flexibility of the digital mask, it is limited in its ability to directly load target layouts that do not meet specific conditions. These conditions include having sizes and intervals that are integer multiples of the pixel size of the SLM, as depicted in Fig. 1(a). This limitation restricts the flexibility of DPML and poses a challenge in achieving the desired device performance, as the resist pattern needs to closely resemble the target layout. Loading the modulation coefficient based on the target layout, as shown in Fig. 1(a), can result in distortion of the resist pattern due to the OPE. This distortion deviates significantly from the intended target layout. To address this issue, DILT optimizes the modulation coefficients of various digital masks, and its flow chart is shown in Fig. 1(b). It's worth noting that the target layout is not limited to sizes and pitches that are integer multiples of the SLM pixel size. DILT allows for the reverse-design of modulation coefficients for target layouts with continuous line widths and periods. The principle behind DILT is to find the optimal modulation coefficient M for a given target layout, ensuring that the photoresist pattern closely resembles the target layout, as shown in Fig. 1(b). This enables high-fidelity photolithographic transfer of target layouts with continuous line widths and pitches. By loading the optimized modulation coefficient, the resulting resist pattern closely matches the target layout, improving the printability of the desired design, as demonstrated in Fig. 1(c).

The modulation of a light field by a physical mask differs significantly from that of a digital mask. In the case of physical masks, optical proximity correction (OPC) techniques have been widely employed [19,20], resulting in curved physical masks [21,22]. However, the increased complexity of these masks significantly raises their manufacturing costs. Consequently, considerable efforts have been made to enhance the manufacturability of optimized physical masks [23–26]. Additionally, since physical masks are fabricated using variable electron beams, their edges are typically considered arbitrary. On the other hand, digital masks have a predetermined pixel size that cannot be altered. The mask function of a digital mask is implemented through the modulation coefficient loaded onto it. DILT offers a reverse-design approach for different types of SLMs, taking into account the constraints of various modulation ranges. In Fig. 1(c), DILT optimizes each pixel of the DMD-SLM to determine whether it participates in the imaging process. For grayscale amplitude LCOS-SLM, DILT inverse designs the grayscale amplitude of each pixel, as depicted in Fig. 1(c). At the same time, it is worth mentioning that DILT will not introduce additional costs for DMPL.

2.3 Method of the DILT

The DILT optimize the information loaded on the SLM. By given a target pattern $\tilde{Z}$, the purpose of DILT is to find the modulation coefficient M loaded on the SLM, so that the distance between the resist pattern and the target layout is the smallest. For LCOS-SLM, the modulation coefficients are normalized between 0 and 1. For DMD-SLM, the modulation coefficients are limited to 0 or 1. In order to make the DILT optimization get the modulation coefficients to be discrete 0 or 1, we need to add a binary penalty term for the mask to the cost function:

The value of the modulation coefficient is limited to the range 0 to 1. Due to the difficulty of constrained optimization, trigonometric functions can be used to transform the problem into an unconstrained optimization problem. Modulation coefficient M can be described by:

In this way, the modulation coefficient M can be optimized indirectly by optimizing the value of the latent variable θ. Solving the problem as described in Eq. (6) can use the gradient descent algorithm which requires computing the gradient of the variables with respect to the cost function. With the help of automatic derivation function of the Pytorch [27], the process of obtaining the value of the cost function through forward propagation will generate a calculation graph. During the backpropagation process, the derivative of the objective function relative to the latent variable θ will be automatically calculated. The derivation of the gradient expression can refer to the Appendix. The specific process of DILT based on Pytorch is given in Algorithm 1.

Algorithm 1. Pytorch-based implementation of the DILT

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2.4 Methods for evaluating performance of DILT

In order to facilitate the evaluation of the optimization effect of the DILT we define the pattern error (PE) as follow:

3. Results analysis and discussion

3.1 Parameter setting

In this paper, the projection imaging system used is based on the parameters of the classic digital mask projection system [2]. The system employs an on-axis point light source illumination with polarization in the x direction and wavelength of 400 nm. The numerical aperture (NA) of the projection imaging system is 1.45, and the refractive index in the object space (such as digital masks in SLM) and the image space (such as pattern on the photoresist film) is 1.0 and 1.516, respectively. Subsequently, the optical projection system reduces the image size by a factor of 100 and projects it onto the silicon wafer, precisely targeting the location where the photoresist is situated.

In order to compare the impact of the amplitude gray scale on the DILT results, the researchers standardized the different types of SLMs to the same size of 5.4 µm, matching the pixel size of the DMD model DLP3010. The sampling interval of the image plane where the silicon wafer is located is set at 3 nm. Thus, the matrix K is constructed with all elements being 1, forming an 18 × 18 matrix. For solving the DILT, a conjugate gradient algorithm [28] is employed as the solver with a step size of 0.001, and the number of iterations is set to 300. When using binary amplitude modulation, the optimized modulation coefficients are quantized to either 0 or 1. On the other hand, for grayscale amplitude modulation, the optimized modulation coefficients are quantized to the nearest grayscale level, using 255 grayscale levels between 0 and 1.

3.2 Pattern optimization of 1D target layout with arbitrary line width

For nanodevice fabrication, achieving the desired line width and pitch is crucial for optimal performance. The DILT plays a significant role in guiding how to apply digital mask modulation to achieve the intended line width and period. The target layout is average-pooled according to the range of pixels of the same digital mask to obtain the initial modulation coefficient [27]. If the target layout aligns exactly with the pixels of the digital mask, binary initial modulation coefficients are obtained, which can be directly loaded onto the DMD. However, if the alignment is not exact, grayscale values are introduced, and this initial setting can only be loaded onto the grayscale modulator.

Firstly, we display the control and optimization of line width in a one-dimensional layout. Figure 2(a) shows the comparison before and after optimization of 1D single-line target layouts with different line widths, including digital mask, and the light field intensity distribution after passing through the projection imaging system. The line width selected for the 1D single-line target layout is from 81 to 135 nm corresponding to 1.5-2.5 pixels of digital mask. The line width change interval is 9 nm, equivalent to adjacent pixel amplitude change 1/6 gray value according to our initial value setting method. However, the presence of the OPE results in a nonlinear relationship between the actual linewidth of the resist pattern and the target linewidth, as depicted in Fig. 2(b). For instance, for the designed layouts with the line width of 99, 108, 117, 126, and 135 nm, the actual resist pattern linewidths at the threshold I_r = 0.5 of the light field do not match the design targets, measuring 51, 84, 90, 102, and 114 nm, respectively. When using the method established in this paper to design the initial modulation coefficient of the pattern with a linewidth smaller than 90 nm, the light field lacks sufficient intensity to adequately expose and retain the resist pattern. As lithography scales shrink, the impact of OPE intensifies, leading to more significant deviations between the actual and expected linewidths.

 

Fig. 2. Pattern optimization of 1D single-line target layout with arbitrary line width. (a) The comparison of digital masks with/without optimization to produce resist patterns with continuously variable line width. The size of a single SLM pixel in the image plane where the photoresist is located is 54 nm × 54 nm; (b) The light intensity profile of single-line layout corresponding to the initial modulation coefficient obtained by grayscale amplitude down-sampling; (c) The light intensity profile of single-line layout corresponding to the optimized modulation coefficient obtained by DILT.

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In the above line width optimization scheme, we can adjust the line width for small changes by controlling the exposure dose. But unfortunately, it is impossible to optimize the different exposure line widths under the same exposure dose or exposure threshold, and it is necessary to introduce gray scale amplitude adjustment of digital mask pixels. To achieve the exposure of different linewidth patterns at the same exposure threshold (i.e. laser power), it is necessary to reverse engineer the loading modulation coefficient. This will enable fine-tuning and adjustment to compensate for the OPE, ensuring the desired linewidths are accurately obtained during the lithography process. DILT addresses this issue by enabling more precise control of the light field and the intensity distribution through accurate manipulation of the modulation coefficient amplitude's gray scale. Figure 2(c) shows the optical field intensity for 1D target layout with arbitrary line width optimized by inverse design. At the light intensity threshold I_r of 0.5, the exposed photoresist linewidths are 81, 90, 99, 108, 117, 126, and 135 nm, which are completely consistent with the theoretical design target layout. For the reverse optimization layout, we can choose a smaller grayscale interval to achieve extremely small width changes, such as 1 nm. By doing so, it surpasses the limitations imposed by pixel size in digital masks, allowing the creation of resist patterns with continuous line width, thereby achieving higher precision and performance for nanodevices.

3.3 Pattern optimization of 1D target layout with arbitrary line pitch

Next, we discuss the optimization of line pitch of 1D double-line target layout by the DILT. The physical mask of traditional lithography can usually control the period of the pattern simply by moving the mask continuously, but this is obviously not applicable to the digital mask, because the movement of the digital mask can only be an integer multiple of the pixel size. Figure 3(a) shows the comparison results of optimization / no-optimization of 1D double-line target layouts with continuously changing line pitches, including digital mask, and the light field intensity. The line pitch and width selected for the 1D double-line target layout are 270-324 nm and 108 nm, corresponding to 5-6 pixels pitch and 2 pixels width of digital mask. When the target layout is empirically based on direct average pooling and used as the initial modulation coefficient design, errors in the line width and period may occur, deviating from the original design, as shown in Fig. 3(b). For the designed layouts with the line pitches of 270, 279, 288, 297, 306, 315, and 324 nm, the actual resist pattern line pitches at the threshold I_r = 0.5 of the light field do not match the design targets, measuring 303, 312, 315, 318, 324, 327, and 330 nm, respectively.

 

Fig. 3. Pattern optimization of 1D double-line target layout with arbitrary line pitch. (a) The comparison of digital masks with/without optimization to produce resist patterns with continuously variable line pitch. The size of a single SLM pixel in the image plane where the photoresist is located is 54 nm × 54 nm; (b) The light intensity profile of double-line layout corresponding to the initial modulation coefficient obtained by grayscale amplitude down-sampling; (c) The light intensity profile of double-line layout corresponding to the optimized modulation coefficient obtained by DILT.

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In contrast, DILT allows flexible movement of the peak position by adjusting the gray-scale amplitude of each pixel as shown in Fig. 3(c). Figure 3(c) shows the optical field intensity for 1D double-line target layout with arbitrary line pitch optimized by inverse design. At the light intensity threshold I_r of 0.5, the line pitches of resist patterns are 270, 279, 288, 297, 306, 315, and 324 nm, which are completely consistent with the theoretical design target layout. Similar to the line width optimization, we can also choose a smaller grayscale interval to achieve extremely small pitch changes, such as 1 nm. This capability enables the generation of a resist pattern with a continuous pitch, ensuring higher precision and accurate representation of the desired layout.

3.4 Pattern optimization of 2D target layout

In addition to line width and pitch, we also need to examine the fidelity of 2D arbitrary target layout. Layouts 1 to 5, depicted in Fig. 4(a), originate from 90 nm metal layers with the minimum line width being 108 nm. Layouts 1 to 3 have line width and pitch that are integer multiples of the pixel size of the digital mask. Consequently, these target layouts can be directly loaded onto a binary amplitude modulated DMD-SLM, as illustrated in Fig. 4(b). However, due to the insufficient exposure light intensity caused by OPE as shown in Fig. 4(c), many hot spots appeared as shown in Fig. 4(d), such as line width non-uniformity, rounded corners, line segment shrinkage, and even resist pattern fractures. These problems adversely impact the high-fidelity transfer of the target layout, making it challenging to ensure the design performance of integrated circuits.

 

Fig. 4. No optimization results of the 2D target layouts. (a) The target layout has a size of 3.456 µm × 3.456 µm. The size of a single SLM pixel in the image plane where the photoresist is located is 54 nm × 54 nm. In order to show the relative position of the target layout and the SLM grid, the 64 × 64 SLM pixel grid where the target layout is located is shown; (b) The initial modulation coefficients of digital mask by grayscale amplitude down-sampling; (c) The optical field intensity distribution in photoresist corresponding to the (b); (d) Resist pattern profile versus target. Black edges represent the target layout, gray color blocks represent to the simulated resist pattern corresponding to the modulation coefficient as shown (b).

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Target layouts like layouts 4 to 6 cannot be loaded directly on the SLM because the line width and spacing are not integer multiples of the SLM pixel size, which limits the achievable target layouts. In such case, the target layout is average-pooled as the initial modulation coefficients, but this approach suffers from the limitation that the designed modulation coefficient exists only in grayscale, making it suitable for loading on grayscale modulated SLMs, as shown in Fig. 4(b). However, the resist pattern corresponding to the loaded modulation coefficient cannot guarantee lithographic consistency, as demonstrated in Fig. 4(d).

When fabricating the metasurfaces structure, they are typically used to modulate specific electromagnetic wave properties, and their functions are closely tied to their designed linewidths. Therefore, in cases like layout 6 in Fig. 4(a-d), which has a feature size of 135 nm, the distortion caused by OPE and variations in line width and pitch can impact the functionality of the designed metasurface. Despite being able to calculate the resist pattern corresponding to the loaded modulation coefficient M quickly in the simulation of lithography system, without the guidance of DILT, knowing the appropriate modulation coefficient to achieve the target pattern becomes challenging.

The results of DILT for optimizing binary amplitude modulation coefficients are displayed in Fig. 5(a∼c). As binary amplitude SLM pixels can only be either on or off, their complex amplitude transmittance lacks intermediate grayscale levels. Nevertheless, DILT effectively optimizes the light field distribution on the silicon wafer by optimizing the binary amplitude of each pixel, even when the period and line width of the target pattern are not integer multiples of the SLM pixel size, as shown in Fig. 5(b). This optimization process allows the final resist pattern to closely approximate the target layout. However, due to the binary modulation limitation, the resist pattern's line width and period may exhibit some errors compared to the target layout, as demonstrated in Fig. 5(c). As indicated in Table 1, DILT can reduce the PE by up to 26%. However, due to the binary modulation's lack of degrees of freedom, the PE drops to only about 37% of the original for more complex layouts, such as layout 2. This limitation becomes particularly significant when the feature size of certain local layouts reduces to 108 nm, as shown in Fig. 5(c). At this point, the feature size is already close to the SLM pixel size, further reducing the solution space. Consequently, under the constraint of the limited solution space, there may still be local pattern errors at the edge of the resist pattern, despite the cost function's objective to minimize the average pattern error and approach the target layout.

 

Fig. 5. Optimization results of the 2D target layouts by DILT. (a) Binary amplitude optimization of digital mask. When the amplitude modulation is limited to 0 or 1, the optimized modulation coefficient obtained by DILT; (b) The optical field intensity distribution corresponding to the (a); (c) Resist pattern profile versus target for binary amplitude optimization of digital mask. Black edges represent the target layout, gray color blocks represent to the simulated resist pattern corresponding to the modulation coefficient as shown (a); (d) Gray amplitude optimization of digital mask. When the amplitude modulation is limited to 0 to 1, the optimized modulation coefficient obtained by DILT; (e) The optical field intensity distribution corresponding to the (d); (f) Resist pattern profile versus target for gray amplitude optimization of digital mask. Black edges represent the target layout, gray color blocks represent to the simulated resist pattern corresponding to the modulation coefficient as shown (d).

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Table 1. Comparison of the PE/nm² with different type digital mask

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The results of DILT optimization using grayscale amplitude modulation coefficients are presented in Fig. 5(d∼f). By optimizing the grayscale amplitude modulation coefficient, the PE is significantly reduced, dropping to about 6.7% on average, compared to the original 29% when using binary amplitude modulation. This substantial reduction in PE enhances the printability of the target layout, achieving better fidelity in reproducing the desired pattern. The introduction of amplitude grayscale significantly increases the degree of freedom for the digital mask light field, thereby expanding the solution space and improving high-fidelity transfer of target layouts. The results clearly demonstrate that our proposed DILT successfully optimizes the digital mask modulation coefficients, closely approximating the target layout and effectively preserving its original function. At the same time, DILT automatically modulates the grayscale of pixels at a certain spacing from the main pattern, as shown in Fig. 5(d). This is similar to sub-resolution assist features [29] and often helps to expand the process window of the pattern and increase robustness against defocus and exposure power fluctuations, even introduce more light intensity distribution in more non-target layout areas.

In general, DILT provides an effective tool for establishing a connection between the target design layout and digital mask modulation coefficients, facilitating the application of DMPL in the manufacturing of integrated circuits or micro-nano devices.

4. Conclusion

In summary, we have developed a DILT to design the modulation coefficient of the digital mask in SLM-based projection lithography systems. By utilizing DILT to design the modulation coefficient, it becomes possible to obtain a resist pattern with consistent line width and pitch, effectively correcting the optical proximity effect and ensuring the desired performance of the device. In the reverse design of binary amplitude modulation coefficient of DMD-SLM, the PE can be reduced to the original 0.26. Furthermore, with gray amplitude modulation of LCOS-SLM, the PE can be significantly reduced to 0.05, greatly enhancing the high-fidelity transfer of the target layout. The versatility of our framework allows for future extensions, such as applying it to the reverse design of phase for LCOS-SLM that possess phase modulation functions. As the framework is combined with accurate lithography modeling in actual production processes, DILT becomes even more effective and precise in reverse engineering the modulation coefficient of digital masks, supporting the performance design of various devices. In the future, DILT has the potential to advance further and enable the reverse design of both amplitude and phase modulation, adding to its versatility and applicability in the field of device design and fabrication.