1. Introduction

Routers in a packet switched network perform a host of processing functions on each packet’s header aimed at ensuring that the packet is correctly forwarded through the network, data integrity is maintained and network management is performed efficiently. Currently, this processing is performed entirely in the electronic domain. As an alternative technology, optical signal processing is being explored, leveraging the high speed and parallelism offered by non-linear optical devices.

A broad range of optical logic gates [1–4], higher-level processing modules [5] and subsystems for performing functions like header recognition, time-to-live decrementing, and parity checking [6] have been investigated. All-optical implementations of many routing functions may benefit from the development of optical half/full adders. One such function is “checksum verification/calculation”, performed by a router on incoming packets to ensure data integrity. For typical IP packets, the checksum is a 16-bit field that contains the one’s complement of the one’s complement sum of all the 16-bit words that make up the packet [7]. As a result, addition of all the 16-bit words including the checksum results in a 0. A router performs this addition on each incoming packet (checksum verification). If the result of the addition is a non-zero number, the router assumes data corruption, and the packet is dropped.

Various designs for all-optical half adders have been proposed, including: (i) using two semiconductor laser amplifiers in a loop mirror (SLALOMs), one configured as an AND gate and the other as an XOR gate [8], (ii) using three terahertz optical asymmetric demultiplexers (TOADs), one acting as an AND gate and the other two configured to provide the XOR output [9], (iii) using four semiconductor optical amplifiers (SOAs), two of them integrated into a Mach-Zehnder interferometer AND gate and the other two generating the XOR output [10], and (iv) using two SOAs, one as the active element in an exchange bypass switch (to generate the AND and OR outputs) and the other in an ultrafast nonlinear interferometer configuration to generate the XOR output [11]. Since the generation of the Sum output (XOR gate) requires dual-rail logic, all these proposals involve interferometric configurations. Though fairly low switching energies can be achieved, stability and dynamic range of the configurations is a concern. Moreover, some of these techniques require additional lasers to carry the output information.

In this paper, we demonstrate an all-optical half adder that is based on only two non-linear optical elements and does not require any additional control signals. To design the half adder, we follow an electronic equivalent circuit that avoids the use of an XOR gate, obtaining the function through the use of more basic gates that are simpler to implement in the optical domain. We use difference frequency generation (DFG) in a periodically poled lithium niobate (PPLN) waveguide to perform the AND operation which generates the Carry output and cross-gain modulation (XGM) in an SOA to imitate an XOR gate that generates the Sum output. Measurements on RZ data show power penalties of <1 dB for the Carry output and <2 dB for the optimally-filtered Sum output.

2. Half adder design

A half adder operates on a pair of input bits and generates two corresponding output bits - the Carry bit (the logical AND function) and the Sum bit (the logical XOR function), as shown in Fig.1. We follow the schematic shown in Fig. 2(a) that uses elementary gates to achieve the XOR functionality. As shown in Fig. 2(b), the optical equivalent circuit uses only two nonlinear optical elements and is easy to construct.

 

Fig. 1. Logic diagram and truth table for a half adder. The Carry output is ‘on’ only when both the inputs (A and B) are ‘on’ corresponding to the AND operation between A and B. The Sum output is ‘on’ if and only if one of the two inputs is ‘on’. This is equivalent to the XOR operation between A and B.

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Fig. 2. (a). XOR-less equivalent circuit for the half adder. (b). Optical schematic for the half adder. A PPLN waveguide performs the AND operation while the SOA simulates the NOT and AND gates operating together to generate the XOR output.

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Signal propagation through the module is depicted in Fig. 3. The two incoming bit-synchronized data streams enter the AND gate (PPLN waveguide) which generates the Carry signal via DFG [12]. One of the input signal wavelengths (λ₁) coincides with the PPLN waveguide’s pump (or phasematching) wavelength. The device employs a χ⁽²⁾ : χ⁽²⁾ nonlinear process to shift the data on the other signal wavelength (λ₂) to a new wavelength, λ_c ≈ 2^*λ₁ - λ₂. Since the conversion occurs only when the pump power is high, the data on the converted wavelength, λ_c is the logic AND of the incoming data on λ₁ and λ₂. DFG is an ultra-high speed process with a wide operational bandwidth of ~ 50 nm for the 6-cm-long device used in this work. Moreover, the PPLN waveguide has negligible spontaneous emission noise and no intrinsic chirp.

The incoming data streams are also coupled into the SOA as low power ‘probe’ signals. The Carry output from the previous stage is amplified and injected into the SOA as a higher power ‘pump’ signal. Whenever the Carry signal is ‘on’ it reduces the SOA’s gain (due to XGM [13]) causing the other signals propagating through the SOA at that time to be suppressed.

 

Fig. 3. Signal propagation through the half adder module. The two inputs are coupled into the PPLN waveguide and the Carry signal is generated at a new wavelength through the DFG process. The Carry signal is amplified and injected into the SOA as a pump signal. Whenever the Carry is ‘on’, it squelches the SOA’s gain and the corresponding input pulses passing through the SOA are suppressed. Only those pulses, which do not have a corresponding Carry pulse, emerge at the SOA output. This is equivalent to an XOR operation and generates the SUM output.

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As a result, the SOA output is ‘off’ whenever the Carry is ‘on’. On the other hand, if the Carry signal is ‘off’, the output of the coupler (OR gate) propagates through the SOA, gets amplified and emerges at its output port. This is equivalent to inverting the Carry output and performing an AND operation between the OR gate output and the inverted Carry output. Therefore, input bit combinations of 00, 01 and 10 will result in 0, 1 and 1 outputs respectively, while a 11 input will be converted to a 0 at the SOA output. This input-output relationship corresponds to an XOR operation and generates the Sum\for the half adder.

3. Experimental setup and results

The experimental setup for the half adder is shown in Fig. 4.

 

Fig. 4. Experimental setup for the all-optical half adder. The PPLN waveguide acts as an AND gate to generate the Carry output. The Carry output saturates the SOA’s gain preventing the corresponding input pulses on λ₁ & λ₂ from emerging at the Sum output port, thereby imitating an XOR gate.

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The data streams are obtained by externally modulating two DFB lasers (λ₁=1550.15 nm & λ₂=1548.53 nm) with 5 Gb/s RZ patterns. The incoming data streams are amplified to 11 dBm, filtered (to suppress ASE noise) using 0.6 nm bandwidth filters and coupled into the PPLN waveguide using a 50:50 coupler. Through DFG, the data on λ₂ is shifted to a new wavelength, λ_c ≈ 2^*λ₁ - λ₂ = 1551.76 nm, whenever the signal on the pump wavelength (λ₁) is ‘on’, thereby providing the AND functionality. The PPLN wavelength conversion spectrum is shown in Fig. 5(a). An optical band-pass filter with a bandwidth of ~0.7 nm is used to filter out λ_c forming the Carry output [Fig. 5(b)].

 

Fig. 5. (a). Output spectrum of the PPLN waveguide. Signal on λ₂=1548.53 nm is converted to λ_c=1551.76 nm when the signal on λ₁=1550.15 nm is high (logic 1). This is equivalent to an AND operation between the signals on λ₁ & λ₂. (b) The converted signal is filtered and amplified forming the Carry output and is also injected into the SOA as a high power pump.

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The second output of the coupler (attenuated to -9 dBm) is fed into the SOA through an isolator. This signal exhibits three power levels corresponding to the 00, 10(or 01), and 11 cases of the logic levels of the two input bits. However, the 11 case is unimportant since it results in the Carry being ‘1’, which saturates the SOA, preventing the coupler output from emerging at the Sum port. The Carry output from the PPLN waveguide is amplified to ~7 dBm and injected into the SOA in the counter-propagating direction via a circulator. An optical delay line is used to synchronize the bits from the OR gate to the corresponding Carry bits inside the SOA. When the Carry signal is ‘1’ (11 input) it saturates the SOA, suppressing the output at the circulator’s port 3, resulting in a ‘0’ for the Sum output.

When the Carry signal is ‘0’ the logical output of the Sum port is the same as that of the OR gate. This can either be a ‘1’ on λ₁ (10 input), a ‘1’ on λ₂ (01 input) or a ‘0’ (00 input). The Sum output is filtered using a ~1.4 nm band-pass filter centered between λ₁ and λ₂. Ideally, a WDM filter should be used to suppress the ASE noise that exists in the spectral region between λ₁ and λ₂. To enhance the performance of the second stage, a reservoir CW signal (1539 nm) at a power of -2.8 dBm is also coupled into the SOA to optically bias the gain, close to saturation. This helps reduce the SOA’s gain recovery time, enabling higher speed processing. The spectrum of the SOA inputs and the XOR output are shown in Fig. 6.

 

Fig. 6. (a). Spectrum of the input to the SOA. The coupler’s output contains pulses on λ₁=1550.15 nm and λ₂=1548.53 nm that are injected into the SOA. A reservoir CW channel, λ_cw=1539 nm optically biases the SOA into saturation. (b) SOA output (Sum) spectrum after filtering at circulator’s port 3. The Sum is comprised of pulses on λ₁ and λ₂ which are filtered together using a 1.4 nm bandpass filter centered between λ₁ and λ₂.

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SOAs optimized for fast gain recovery time (<20 ps) have been shown to be feasible for 40 Gb/s processing [14]. If cross polarization modulation is used in the proposed module instead of XGM, it may be possible to employ the differential mode of operation [15] to further enhance the frequency response. Since the DFG in a PPLN waveguide is an ultra-high speed wave-mixing process (> THz bandwidth), the overall speed of the half adder is determined by the XGM stage and is therefore limited by the gain recovery time of the SOA used. Recent work on filtering-assisted XGM [16] has achieved bit-rates of 320 Gb/s.

Sum and Carry output bit streams, shown in Fig. 7(a), exhibit extinction ratios in excess of 14 dB. The combined Sum output obtained by centering the output filter between λ₁ and λ₂ is noisier than the Sum outputs on individual wavelengths due to unfiltered ASE noise between the wavelengths. Figure 7(b) shows the BER curves and eye diagrams for the input data, Carry output and the Sum output. The curve for the Sum output on λ₁ is also included since this represents the power penalty if a WDM filter is used at the SOA output. The Carry output and the Sum output on λ₁ show approximately 1 dB and 2 dB power penalties, respectively. An extra 1.8 dB penalty for the combined Sum output is due to unfiltered ASE noise.

Compared to other techniques [9,10], our design reduces the overall active component-count to only two elements by using the output of the first stage as a control signal in the second stage. No additional lasers are required since the XOR output appears on the input wavelengths and the AND output is generated on a new wavelength by nonlinear mixing of the input signals. The module’s performance can be improved by using a PPLN waveguide with higher conversion efficiency, thereby reducing the overall switching energy/pulse. Other techniques to generate an AND signal can be used instead of the PPLN waveguide, leading to reduced polarization dependence. A degenerate wavelength AND gate can be constructed by using cross-absorption modulation in an electro-absorption modulator [1]. This may enable the half-adder to operate with both inputs on the same wavelength, leading to a single-wavelength Sum output. Further, if the first stage (AND gate) is configured as an optical switch wherein one of the input signals acts as the control for switching the other input [1], it may be possible to obtain the Carry output on the same wavelength as the Sum.

 

Fig. 7. (a). 5 Gb/s RZ bit patterns for the half adder. The Carry output is ‘on’ only when both the inputs are ‘on. Pulses on λ₁ (λ₂) emerge at the SOA output only if they do not have a corresponding pulse on λ₂ (λ₁). These two wavelengths are filtered together to obtain the Sum output. (b) BER measurements for the half adder. The Carry output exhibits <1 dB power penalty while the Sum output on a single wavelength shows <2 dB penalty. The excess penalty of the combined Sum output is due to unfiltered ASE noise.

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4. Conclusion

We demonstrated an all-optical half adder to perform binary addition of two data streams using only two nonlinear optical elements. The module acts on pairs of input bits, enabling bit-wise serial half addition that results in a Carry bit and a Sum bit. A PPLN waveguide is used as an AND gate and an SOA is used to perform the XOR operation required to generate the SUM output. Error free performance is achieved for RZ data with <2 dB power penalty.