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This study proposes a novel packaging structure for vertical thin-GaN LED applications by integration of LED chip and silicon-based packaging process. The vertical thin film LED is directly mounted on package submount. The shortest thermal path structure from junction to package submount achieves the lowest thermal resistance of 1.65 K/W for LED package. Experimental results indicate that low thermal resistance significant improved forward current up to 4.6A with 1.125 × 1.125 mm2 LED chip size.
© 2014 Optical Society of America
Corrections
Shih-Yi Wen, Hung-Lieh Hu, Yao-Jun Tsai, Chen-Peng Hsu, Re-Ching Lin, and Ray Hua Horng, "A novel integrated structure of thin film GaN LED with ultra-low thermal resistance: erratum," Opt. Express 22, A960-A960 (2014)https://opg.optica.org/oe/abstract.cfm?uri=oe-22-S3-A960
1. Introduction
High-power GaN-based LEDs are promising candidates for the application of next-generation general lighting because their wall-plug efficiency is comparable to conventional fluorescent lamps. Recently, LEDs with a vertical structure, or vertical LEDs (VLEDs), have been widely researched as a high-potential replacement for conventional LEDs manufactured with sapphire substrates. However, there are still many obstacles to overcome and improvements to be made, particularly the heat dissipation and light output power issues. Currently, there are several approaches to increase LED light output power, including transparent contact layers [1], patterned sapphire substrates, and surface texturing [2]. Although these methods could improve LED light output by increasing light extraction efficiency, these LEDs suffer from power limitation when driven at higher input power levels. It is necessary to drive the LEDs to high current density level to achieve larger light output power. However, in this circumstance, the LEDs typically exhibit the performance deterioration in terms of power saturation. In conventional LEDs with sapphire substrates, p- and n-electrodes must be placed on the same side, and, consequently, current and heat crowding around the electrodes result in lower internal quantum efficiency (IQE) because of the poor thermal conductivities of sapphire (35 W/mK) and conventional die-bonding material of silver paste [3]. Several schemes have been proposed to enhance the heat dissipation of the sapphire-based LEDs for high-power applications [4–8]. VLEDs, however, allow an epitaxial layer to form between two metal electrodes to adhere to submount substrates. Because currents travel to the submount substrates vertically through n-GaN, VLEDs have a more uniform current density distribution and can be operated at higher injection powers compared with conventional structures [9–12]. Several approaches have been proposed to enhance the heat dissipation of the VLEDs [13–15]. However, chip carrier and more high temperature bonding process and thermal interface limit further reduction of thermal resistance.
In this study, a novel thin-film LED packaging (TFP) structure is proposed to minimize thermal resistance of high power LEDs. The schematic structure is shown in Fig. 1, the layered LED epitaxial thin-film is directly bonded to packaging submount through the p-GaN pad. The n-GaN pad is wire-bonded to bonding pad on submount to form a vertical type current injection. Comparing to conventional thin-GaN LED, the thermal path from LED junction to submount is decreased to minima due to the elimination of chip-carrier and first bonding layer. In the following sections, fabrication process and experimental results will be discussed in detail.
2. Experiments
The whole fabrication process of TFP can be divided into three parts, first is TFP-chip process, second is TSV-submount and third is the integrated packaging process. The TFP-chip process is similar to the front-end process of conventional vertical thin-GaN LED chip. Once finish metallization of p-GaN, the chips are diced from sapphire wafer. Here, the structure of TFP-chip is 150μm-thick sapphire substrate, epitaxy LED layers, Ni/Ag/Ni mirror layers, Cr/Pt/Au barrier layers and 2.5 μm-thick Au80Sn20 bonding layer. The silicon packaging submount is 400μm in thickness. The through-silicon vias (TSV) are fabricated by double side KOH anisotropic wet etching to achieve square via opening of 350μm in length. After thermally grown of silicon dioxide layer on whole surfaces of silicon submount wafer, the vias are filled with silver paste. Finally, the traces and bonding pads on both sides of submount wafer are electroplated with total 10~15μm thick Ti/Cu/Ni/Au metal layers.
The integration packaging process is shown in Fig. 2. Figure 2(a) shows the prepared TFP-chip is mounted on the TSV-submount using eutectic bonding with maximum temperature of 320°C in reflow profile. Figure 2(b) shows the sapphire substrate of TFP-chip is removed using a laser lift-off process by 248nm-KrF excimer laser. The residual product Ga is removed from the GaN surface by rinsing in diluted HCl:H2O Π1:1| solution for 60 seconds. Following, the undoped GaN layer was etched off by inductively coupled plasma (ICP) etching system to expose the n-GaN layer as shown in Fig. 2(c). Then the 1.5μm-thick Cr/Pt/Au layers as n-GaN electrode and bonding pad are deposited in sequence on the exposed n-GaN layer, as shown in Fig. 2(d). After wire bonding and silicone lens molding, the surface-mountable TFP is finished, shown in Figs. 2(e) and 2(f). Figure 3 shows photograph of the as-fabricated TFP with a light-emitting area of 1.125mm × 1.125 mm and package size of 3.5mm x 3.5mm.
Fig. 2 Integration packaging process flow of TFP LED, (a) chip to wafer eutectic bonding, (b) laser lift-off and Ga remove, (c) U-GaN etching, (d) N-pad metallization, (e) wire bonding and (f) lens molding and singulation.
During integration packaging process, shear testing is performed by DAGE bond tester followed MIL-STD-833 method 2019.5 to determine the bonding strength of TFP-chip. The current-voltage characteristics and leakage current test that measures the low-level current that leaks across the LED when a reverse voltage less than the breakdown are applied at room temperature using an Agilent 4155B semiconductor parameter analyzer. Light output power of TFP and LEDs for comparison are measured by an integration sphere (CAS 140B, Instrument Systems). A thermal transient tester (T3Ster Master system) is used to measure total thermal resistance of TFP based on thermal transient analysis.
3. Results and discussion
In order to ensure the thin-film structure can be reliably adhered firmly to the packaging submount, eutectic die bonding using gold-tin solder is a highly reliable technique to meet the requirement and benefits good thermal conductivity. For gold-tin eutectic die bonding, there are currently two possible approaches, namely flux eutectic bonding and direct eutectic bonding. To achieve high bonding strength, both approaches are employed with sophisticated heating and cooling mechanisms to study a better bonding process for TFP. During flux eutectic bonding, a small volume of flux is placed on the submount, and the TFP-chip is placed onto the flux. After that, the substrate with multiple TFP-chips mounted on it will be put into the reflow oven with four heating zones to complete the bonding. There is no external force applied throughout the process. Direct eutectic bonding involves preheating the submount then multiple TFP-chips are picked and placed onto the heated submount. Then the submount is transfered to a wafer-to-wafer bonder and an average compression pressure about 3MPa is uniformly applied on the TFP-chips through a soft graphite sheet. Then proceed the heating and cooling procedure in a 10−2 torr vacuum environment.
The shear test results of both bonding approaches are shown in Table 1.The average die shear force of flux eutectic bonding is 3.08Kgf. However, the average die shear force is 7.78Kgf for direct eutectic bonding that shows superior bonding quality. The higher bonding strength results in reduction of voids in the bonding layer and higher yield after laser lift-off process and less thin-film structure breakage. In addition, it is very helpful for obtaining lower thermal resistance of TFP.
Table 1. Shear force test results of different eutectic bonding process.
Figure 4 shows results of leakage current test after finish of n-GaN metallization in the integration packaging process. A reverse voltage of 5 volts is applied to the total fabricated 106 pieces TFP LEDs on packaging submount wafer. Among test samples, 77% of TFP LEDs show leakage current below 0.1μA. The laser lift-off process is conducted after low void chip-to-wafer bonding bonding process that helps to release large stresses generated more easily. In addition, LED structure grown on non-PSS “flat” sapphire and appropriate underfill material to cushion the stress caused by LLO are also helpful for yield improvement.
By model of series thermal resistance, the thermal properties in each layer of LED package could be derived in the transient thermal resistance measurement. Therefore, the positions of defects cause thermal accumulation in the package could be identified from measurement results. Here we use T3ster made by MicReD to analyze the thermal characteristics of the fabricated TFP surface mounted on metal-core PCB test board with SnAgCu solder. Thermal grease is applied between test board and heat sink with cooling system. The temperature sensitivity coefficient (Temperature Sensitive Parameter, TSP) is determined by measurement of the LED voltage changes at different temperatures from 25~75 °C. Then applying test currents to calculate the corresponding junction temperatures based on TSP. Through convolution theory, Bayes iteration [16], the thermal impedance structure is obtained from the change of junction temperatures.
Figure 5 shows the differential structure functions of the TFP with different bonding condition and commercial high power LED products with different 45mil LED chip structures. It can be interpreted that the heat capacity rises at every thermal interface which causes thermal accumulation. The peak of heat capacity could be used to determine the position of material interface and the difference of corresponding thermal resistance values between the peaks represents the thermal resistance of material. Figure 5(a) is the differential structure function for TFP fabricated with direct eutectic bonding. The thermal resistance from junction to package submount is estimated to be about 1.65 K/W where the thermal resistance of the LED epitaxial layer and bonding metal layer are about 0.74 K/W and 0.56 K/W respectively. As for comparison, Fig. 5(b) shows the differential structure function of TFP fabricated with flux eutectic bonding, the thermal resistance of bonding metal layer significant increases to 0.88 K/W due to moderate bonding quality resulting in more heat accumulation in the LED package. The measured thermal resistance of TFP with direct eutectic bonding is significant lower than that of commercial high power LED packages which typically are in the range of 5.0~10.0 K/W as shown in Figs. 5(c) and 5(d).
Fig. 5 Thermal resistance measured by T3ster (a) TFP with direct eutectic bonding; (b) TFP with flux eutectic bonding; (c) commercial face-up LED package and (d) commercial thin-GaN LED package.
So far, we can conclude that the LED epitaxial thin-film directly bonded on packaging submount helps significantly in improving thermal resistance due the reduced thermal path. Now, we further characterize the behavior of optical output power at different forward current. Figure 6 shows the test results compared to the conventional high power LED packages with horizontal type LED chip and thin GaN LED chip. The light outputs for each test sample are all normalized at 350mA. From results, the output power of TFP is saturated at high current operation of 4.6A (Vf~5.6 volts) while conventional vertical thin-GaN LED package is saturated at lower current level of about 3.9A (Vf~4.8 volts). Where the test samples are mounted on the same test board and the current conditions are pulse width 200ms and duty ratio 50%. The test pulse currents is continuous applied, therefore heat accumulation would happen on the chips of all test samples. Owing to TFP has the lowest thermal resistance, and thus enhance the capability for high current operation. The reduction of heat accumulation significantly enhanced the optical and thermal characteristics of the TFP LEDs. Of course, better current spreading condition than horizontal type LED also helps.
4. Conclusions
This study developed a novel integrated structure of 1.125mm x 1.125mm thin-film GaN LED package. Different from conventional packaging structure and process, we proposed an integration process that processing vertical thin film LED chip fabrication on packaging submount with TSV. The epitaxial thin film LED structure is bonded directly on submount and shows superior thermal conductivity to a significantly low value thermal resistance of 1.65 K/W. In addition, the saturation current of TFP is characterized and compared to commercial packages with different types of LED chip. The capability to high forward current level up to 4.6A indicates the TFP is very suitable for etendue limited lighting applications such as spot light, automotive headlamp and fiber light.
Acknowledgment
This work was supported by the Department of Industrial Technology (DoIT) of Ministry of Economic Affairs (101-EC-17-A-04-01-0310).
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