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We propose and evaluate an all-optical 2-bit header recognition and packet switching method using two 1.55-µm polarization bistable vertical-cavity surface-emitting lasers (VCSELs) and three optical switches. Polarization bistable VCSELs acted as flip-flop devices by using AND-gate operations of the header and set pulses, together with the reset pulses. Optical packets including 40-Gb/s non-return-to-zero pseudo-random bit-sequence payloads were successfully sent to one of four ports according to the state of two bits in the headers with a 4-bit 500-Mb/s return-to-zero format. The input pulse powers were 17.2 to 31.8 dB lower than the VCSEL output power. We also examined an extension of this method to multi-bit header recognition and packet switching.
© 2015 Optical Society of America
1. Introduction
Many-types of optical signal processing have been investigated for optical packet switching [1]. The all-optical packet switching method based on wavelength labelling was reported [2,3]. With this method, 1 × 4 switching by 2-label recognition was demonstrated for a 160-Gb/s return-to-zero (RZ) data signal. Although the number of labels is limited due to deterioration of the optical signal-to-noise ratio (OSNR), the possibility of extension to 1 × 256 switching by 8-label recognition was discussed [2]. The optical digital-to-analog converter method [4] was also proposed for high-speed operation, and 2-bit header recognition and packet switching were demonstrated, although the signal-to-noise ratio deteriorated with increasing header length. High-speed label switching using a multimode interference bistable laser diode was demonstrated with 1-bit header recognition [5,6], but extension to multi-bit header recognition was not reported.
We have been investigating all-optical signal processing using polarization bistable vertical-cavity surface-emitting lasers (VCSELs). We demonstrated an operation of 4-bit optical buffer memory, which stored and regenerated 4 bits of 500-Mb/s RZ data using four 1.55-μm VCSELs [7]. Next, we reported fast operations of a memory in which one bit was arbitrarily selected from a 20-Gb/s RZ pseudo-random bit-sequence (PRBS) data signal and a 40-Gb/s non-return-to-zero (NRZ) data signal then stored using a 980-nm VCSEL [8]. In these operations, polarization bistable VCSELs acted as flip-flop devices by using AND-gate operations of the data and set pulses, together with the reset pulses. After that, we applied the flip-flop operation with AND-gate functionality to optical header recognition by using a 1.55-μm VCSEL and successfully demonstrated optical packet switching, where the optical packets including payloads with a 500-Mb/s RZ PRBS format [9] and a 40-Gb/s NRZ PRBS format [10] were sent to one of two ports according to the state of one bit in the 4-bit header with the 500-Mb/s RZ format. This method is advantageous in extending to multi-bit header recognition. Separation of the header and payload is not necessary for optical header recognition, in contrast to other studies [2–6] based on header-payload separation.
In this letter, we propose and evaluate a header recognition and packet switching method by using two VCSELs to show that this header recognition method based on the flip-flop operation with AND-gate functionality [8,9] can easily be extended to multi-bit header recognition. Two arbitrary bits were recognized from a 4-bit header with the 500-Mb/s RZ format and optical packets including payloads with the 40-Gb/s NRZ PRBS format were sent to one of four ports according to the states of two bits.
2. Principle of optical header recognition and packet switching
A polarization bistable VCSEL with a square mesa structure has two lasing modes with polarization directions orthogonal to each other (0° and 90°). If an optical signal with sufficient power and the polarization direction orthogonal to that of the lasing mode is input into the VCSEL, the lasing polarization state is switched. The switched state is maintained even if the optical signal is cut off. Thus, the polarization bistable VCSEL can act as a flip-flop device by using optical pulses with 0° and 90° polarizations. The flip-flop operations with AND-gate functionality can be achieved using a polarization switching threshold characteristic of the VCSEL.
Figure 1(a) shows an implementation to illustrate the operation principle of the optical header recognition and packet switching based on the flip-flop operation with AND-gate functionality. A data signal (i.e. optical packet) is composed of a header and a payload. The data signal and set pulse have 0° polarization and the reset pulse has 90° polarization. These three signals are input into the polarization bistable VCSEL. The VCSEL output through a polarizer with its polarization axis oriented at 0° is input into a control port of an all-optical switch. The length of optical delay line in front of the all-optical switch is adjusted so that optical packets may go through the all-optical switch while the VCSEL 0° output is input into the control port. Figure 1(b) shows a timing chart for the case in which the second bit of the header is recognized. The input powers of both the data and set pulse are set to less than the threshold of the polarization bistable switching of the VCSEL. The set pulse is combined with the second header bit in the data signal then input into the VCSEL whose lasing polarization is 90°. When both a “1” header bit and a set pulse are input into the VCSEL simultaneously, the input power exceeds the switching threshold, and the lasing polarization of the VCSEL is switched from 90° to 0°. When a “0” header bit and a set pulse are input, the lasing polarization is not switched. Thus, the lasing polarization state is determined to be 0° or 90° according to the state of the header bit (“1” or “0”), and the switched polarization state of the VCSEL is maintained until the reset pulse is input. The all-optical switch is controlled by the VCSEL output through the polarizer, and the data signals are sent to one of output ports according to the state of header bit that is recognized.
Fig. 1 Principle of optical header recognition and packet switching based on flip-flop operation with AND-gate functionality using polarization bistable VCSEL. (a) Implementation and (b) timing chart for case in which the second bit of header is recognized.
We previously measured the bit error rate (BER) of flip-flop operation with AND-gate functionality to evaluate its stability [11]. The timing chart of the input pulses and corresponding VCSEL output signals are illustrated in Fig. 2(a). All input pulses had a 1-ns duration, which corresponded to RZ signals at 500 Mb/s. The data pulses had a format of PRBS 211−1, and the set and reset pulses had a repetitive pattern. As a result, a good BER of 5.00 × 10−9 was obtained, and the eye diagram was clearly opened, as shown in Fig. 2(b). A relaxation oscillation was observed at the beginning of the VCSEL 0° output during 2 ns. The operation of all-optical switch may be unstable during the relaxation oscillation. To switch optical packets appropriately by using flip-flop operation with AND-gate functionality, the input timing of optical packet should be delayed from the rise of VCSEL 0° output for about 2 ns by adjusting the length of optical delay line in front of the all-optical switch. In the header recognition method based on the flip-flop operation with AND-gate functionality, relatively low bit rate signals, such as a 500-Mb/s RZ format, can be used for the header because the header is only used to control optical switches, although the payload is generally required to have a signal with a much higher bit rate (for example, 40-Gb/s NRZ). The result of BER measurement indicates that the flip-flop operation with AND-gate functionality using optical pulses with a 500-Mb/s RZ format is suitable for header recognitions. If necessary, operations with a higher bit rate are available. We also demonstrated optical memory operations in which one bit was selected from a 6-Gb/s RZ PRBS data signal and stored by using flip-flop operation with AND-gate functionality [12].
Fig. 2 All-optical flip-flop operation with AND-gate functionality: (a) timing chart and (b) eye diagram with BER of 5.00 × 10−9.
3. Experimental setup and results
We evaluated our all-optical 2-bit header recognition and packet switching method by using two 1.55-μm VCSELs. The timing chart is shown in Fig. 3. The format of the header was 4-bit 500-Mb/s RZ, and that of the payload was 40-Gb/s NRZ PRBS 211−1. The input timing of the set pulse into VCSEL1 (VCSEL2) was adjusted to the second (third) bit of the header. We prepared four different patterns of the second and third bits of the header, and the data signals were sent to one of four ports according to the patterns. Namely, the data signals having headers “1001”, “1101”, “1011”, and “1111” were output from ports 00, 10, 01, and 11, respectively.
Figure 4 shows the experimental setup. The data, set, and reset pulses were generated using a pulse pattern generator, two laser diodes, and three LiNbO3 modulators. The VCSEL outputs were separated into 0° and 90° outputs using polarization beam splitters. The waveforms of 90° outputs were monitored using an oscilloscope and photodiodes (PDs). Since the VCSEL 0° and 90° outputs are almost complimentary, the waveforms close to the 0° output waveforms are obtained by inverting the 90° output waveforms. The PDs converted the VCSEL 0° output signals to electrical signals then the signals were fed into the control ports of three LiNbO3 switches (LNSWs). The output of VCSEL1 (VCSEL2) controlled LNSW1 (LNSW2 and LNSW3). Due to the limitations imposed by our experimental instruments, we used PDs and LNSWs instead of all-optical switches such as semiconductor optical amplifier Mach-Zehnder interferometers (SOA-MZIs). Erbium-doped fiber amplifiers and RF amplifiers were used to obtain suitable signal levels for operation of the LNSWs. Another oscilloscope equipped with PDs measured the output waveforms of data signals from all four ports of the LNSWs. The bias current, output power, and operation temperature were 9.33 mA, −2.5 dBm, and 20°C for VCSEL1, and 8.81 mA, −1.0 dBm, and 18°C for VCSEL2. The VCSEL1 lasing wavelengths were 1551.240 nm for 0° polarization and 1551.130 nm for 90° polarization. Those of VCSEL2 were 1551.244 and 1551.123 nm, respectively.
Fig. 4 Experimental setup for all-optical 2-bit header recognition and packet switching. LD: laser diode, LNM: LiNbO3 modulator, PPG: pulse pattern generator, PD: photodiode, PBS: polarization beam splitter, EDFA: erbium-doped fiber amplifier, LNSW: LiNbO3 switch, 3 dB: optical 3-dB coupler.
The experimental results are shown in Fig. 5. The waveforms of Set1, Reset1, Set2, and Reset2 are not measured results but eye guides indicating the timing of these pulses. The amplitude of VCSEL1 output was smaller than that of VCSEL2 because the output power of VCSEL1 was smaller than that of VCSEL2 by 1.5 dB. The optical packets with headers of “1001”, “1101”, “1011”, and “1111”, were successfully sent to ports 00, 10, 01, and 11 of LNSW2 and LNSW3, respectively. The difference in amplitudes of four output data signals is considered to originate from the difference in the insertion losses of the LNSWs. The input powers of the data, set, and reset pulses were −31.9, −31.7, and −19.7 dBm for VCSEL1, and −32.8, −32.4, and −19.5 dBm for VCSEL2. The input pulse powers were 17.2 to 31.8 dB lower than the VCSEL output power. The optimum frequency detuning of the data and set pulses was −2.6 GHz from the 0° lasing frequency for VCSEL1, and that of the reset pulses was −1.1 GHz from the 90° lasing frequency. Those for VCSEL2 were −2.1 and −2.0 GHz. Because the separation of the header and payload was not required for this header recognition, it was not examined in the experiment. Thus, the data signals output from the optical switches included headers. Headers can be easily eliminated by making the polarization of the header orthogonal to that of the payload and inserting polarizers after optical switches if necessary for header swapping.
Fig. 5 Experimental results of all-optical 2-bit header recognition and packet switching. Waveforms of Set1, Reset1, Set2, and Reset2 are not measured results but eye guides indicating timing of these pulses.
4. Extension for multi-bit header recognition and packet switching
By increasing the number of VCSELs and optical switches, the number of header bits that can be recognized is increased. An example schematic configuration of 4-bit header recognition and packet switching is shown in Fig. 6 together with optical power levels on optical paths. First, the data signal is divided into two, then one is input to a 1 × 4 coupler and the other is sent toward four-stage cascaded SOA-MZIs. The outputs from the 1 × 4 coupler are input to four VCSELs placed in parallel together with set and reset pulses. The outputs of those VCSELs recognizing the header bits are used to control the SOA-MZIs. The VCSEL output power is about 0 dBm in our case, and the required control power of the SOA-MZIs is around 0 dBm (−3.3 dBm [2], and + 7.7 dBm [5]). Both powers are assumed to be 0 dBm. The VCSEL outputs are amplified using semiconductor optical amplifiers (SOAs) to compensate for power reduction due to division of the control power. Note that we consider the case in which VCSEL outputs are amplified before the power division to minimize the necessary number of SOAs. The following performances of SOAs, as described in [13], are assumed for our simulation: (i) the optical gains are 20, 18, and 9 dB for input powers of −20, −12, and 0 dBm, respectively, (ii) saturation input power, i.e., the input power at which optical gain is reduced by 3 dB, is −10 dBm. As the amplified VCSEL output power is limited to + 9 dBm before the power division due to the performance of SOAs, the number of power divisions is limited to eight for feeding 0-dBm control signals into the SOA-MZIs. The SOAs are also inserted into the path passing through the SOA-MZIs to compensate for their insertion loss, which are assumed to be 6 dB [3]. The SOAs are inserted before the first- and third-stage SOA-MZIs, as shown in the figure. As a result, the output powers from the fourth-stage SOA-MZIs are larger than the input power by 11 dB. In this configuration, the total numbers of SOA-MZIs and SOAs are 15 and 8, respectively.
Fig. 6 Schematic configuration of proposed 4-bit header recognition and packet switching. 3 dB, 1 × 4, 1 × 8: optical coupler, SOA: semiconductor optical amplifier, ATT: optical attenuator, VOA: variable optical attenuator. Numbers noted in brackets are optical power levels in dBm.
The OSNR of the control signal deteriorates by passing through the SOA. Because polarization bistable VCSEL output after passing through the polarizer generally has an OSNR larger than 20 dB, the OSNR of the control signal becomes larger than 10 dB if the noise figure of the SOA is lower than 10 dB. We define the OSNR by the difference in power of the signal and noise at a wavelength 1 nm away, as described in [14]. In [2,3], Calabretta et al. argue that the OSNR of the control signal deteriorates when the control signal passes through the SOA-MZIs, which are placed in series for label processing. Therefore, the deterioration of the OSNR of the control signal limits the number of recognized labels. With our proposed method, however, control signals pass through SOAs placed in parallel, as shown in Fig. 6. Thus, the limitation in the number of recognized header bits due to OSNR deterioration decreases compared with the case discussed in [2,3].
As shown in Fig. 6, the data signal passes through six SOAs in total, i.e., two SOAs and four SOA-MZIs. The power of the data signal is −20 dBm before the first SOA. The OSNR of the data signal passes through the SOA and SOA-MZIs also deteriorates. The OSNR was investigated as a function of the number of buffer circulations including four SOAs, and an OSNR of about 20 dB was measured for an input power of −20 dBm after two circulations, which corresponds to pass through of eight times in the SOA [14]. If we assume the same value for the deterioration by an SOA in our configuration, the OSNR is expected to be about 20 dB after passing through the four-stage SOA-MZIs. In this case, the extinction ratio of the data signal would also be about 20 dB, which is better than the measured values of 11–17 dB for the output signals in 1 × 16 packet switching [15], and would be acceptable for the data signal.
If we can reduce the insertion loss in the SOA-MZIs, the OSNR deterioration of data signal would be relieved. In addition, if we can use an integrated SOA array [16] and VCSEL array, the size of this circuit would greatly reduce.
5. Conclusion
We proposed and evaluated an all-optical 2-bit header recognition and packet switching method by using flip-flop operations with AND-gate functionality of two 1.55-µm polarization bistable VCSELs and three optical switches. Optical packets including 40-Gb/s NRZ PRBS payloads were successfully sent to one of four ports according to the state of two bits in the 4-bit header with the 500-Mb/s RZ format. The input pulse powers were 17.2 to 31.8 dB lower than the VCSEL output power. This header recognition method based on flip-flop operation with AND-gate functionality can be applied to different modulation format payloads with different speeds and lengths and can be easily extended to multi-bit header recognition.
Acknowledgments
This work was supported in part by JSPS KAKENHI Grant Number 24226011 and 26420307.
References and links
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