1. Introduction

As we all known, chaotic lasers have been generalized to apply some special fields such as chaotic radar ranging [1], optical reservoir computing [2, 3], chaotic secure communication [4–6], chaotic neural network [7, 8], physical random number [9–11]. They have also potential important applications in chaotic computation [12–14]. Optical chaos computing is a new approach to implementing a logical optic circuit. Since the chaotic laser systems exhibit different behaviors and patterns, they have potential ability to implement different types of optical logic function, and can be used to perform universal computing with appropriate combinations, showing that all possible functions can be programmed. Therefore, it is prospective that optical chaos computing can provide a new optical computer architecture. Moreover, since laser chaos has very abundant dynamic behavior, unpredictability and flexible transformation of behavior mode, compared with typical optical logic computing realized by using nonlinear effects of fiber [15], periodically poled lithium niobite waveguide [16] and semiconductor optical amplifier [17], optical chaos logic computing has more security, flexibility, anti-jamming ability and lower power cost.

Vertical cavity surface emitting lasers (VCSELs) show more advantages than edge-emitting lasers such as small volume, low cost, small threshold current, easy integration and so on, showing that they have great potential application in integrated optical chaotic computing system. When VCSELs are subjected to optical injection or optical feedback, they easily generate chaotic dynamic behaviors of two mutually orthogonal polarization components [18–26]. Using polarization bistability and abundant modes embedded in the chaotic VCSEL system, basic and complex optical logic functions can be programmed. Recently, some theoretical works about optical chaos computing focus mainly on some basic logic operations with the bit time of several nanoseconds. For example, using the polarization bistability of the chaotic VCSEL with optical injection in different setups, Masoller C et al. realized some basic chaotic logic operations, such as AND, OR and NAND [27]. Yan S L et al. implemented some basic logic operations based on the drive-response chaotic laser system, such as XNOR, NOR and so on [28]. Singh and his co-workers verified numerically the phenomenon of logical stochastic resonance in a polarization bistability laser [29]. Our previous works have been focused on controllable basic optical chaotic logic operations with the bit time of 10 ns in an optically injected VCSEL and an optical feedback injected one [30, 31]. In optical chaos computing architecture and the processing of chaotic signals in optical chaotic secure communication network, optical chaotic data-selection, as a complex chaos computing, plays an important role. It is noted that optical chaotic data-selection can be generalized to apply in more complex optical combinational chaotic computing and optical sequential chaotic computing, cooperating with other basic optical chaotic computing. The implementations of these complex chaotic logic computing are conducive to the construction of optical computing architecture, and will promote the practical process of optical chaotic network communication systems.

For all we know, optical chaotic data-selection computing is rarely concerned and no researches on it have been reported. Motivated by this, we propose a new theory mechanism and a novel scheme for the realization of high-speed optical chaotic data-selection computing with the bit time of picosecond magnitude in an optically injected VCSEL, controlling the data-selection logic operation between the frequency detuning and three logic chaotic signals including two logic input signals and one clock signal.

 

Fig. 1 Schematic diagram of two parallel optical chaotic data-selection computing in an optically injected VCSEL (see texts for the detailed description).

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2. Theory and model

Figure 1 shows the implementation of two parallel optical chaotic data-selection computing. Here, a sampled grating distributed Bragg reflector laser (SGDBR), as a tunable laser, produces different central frequencies under different bias currents; the optical isolator 1 (IS₁) is used to avoid the light from the fiber beam splitter 1 (FBS₁) to feedback into the SGDBR. The IS₂ is used to avoid the light from the fiber polarization beam splitter 2 (FPBS₂) to feedback into the VCSEL. The neutral density filter 1 (NDF₁) and the NDF₂ are used to control the strength of two input optical signals, respectively. The strength of the optical clock signal is adjusted by the NDF₃. The polarization controllers (PC₁, PC₂ and PC₃) are used to ensure that the output light ($E_{\text{inj}3}$) and two ones ($E_{\text{inj}1}$ and $E_{\text{inj}2}$) from the FBS₂ have the same polarization. The time delays of different light paths between FPBS₁ and FC₂ are set as the same, and those between FBS₆ and VCSEL are considered to be identical. The light from the SGDBR is separated into two beams by the 1×2 FBS₁. One of the beams is injected into the 1×

2 FBS₅ and the other is separated into two beams again by the 1×2 FBS₂. The two beams of light from the 1×2 FBS₂ are then injected into the 1×2 FBS₄ and 1×2 FBS₃, respectively. Two logical inputs I₁ and I₂ are encoded in the amplitudes of two beams of light separated equally by the FBS₄ and FBS₃, respectively. One beam of light from the FBS₁ is separated equally into two beams by the FBS₅. One beam of light from the FBS₅ is encoded into one optical clock signals, which is defined as I₃. The logic signals I₁, I₂ and I₃ are coupled into one beam by the 3×1 fiber coupler 1 (FC₁). To ensure that arbitrary polarized light from the FC₁ can be parallelly injected into the x-polarization component (x-PC) and y-PC of the VCSEL, it is necessary to convert the arbitrary polarized light into linearly polarized light by some optical passive devices placed between the FC₁ and the FC₂. Here we consider the converted linear polarization light is the x-PC. The arbitrary polarized light from the FC₁ is divided into the x-PC and y-PC by the FPBS₁. The x-PC is directly injected into the FC₂. The y-PC is firstly converted to the x-PC by the faraday rotator (FR₁) and half wave plate (HWP₁), then injected into the FC₂. Thus, the light from the FC₂ is ensured to be the x-PC, which is split into two beams by the FBS₆. One beam is directly injected into the x-PC of the VCSEL, the other is converted into y-PC by the FR₂ and HWP₂, and then injected into the y-PC of the VCSEL. Here, the two chaotic PCs emitted by the VCSEL are encoded into the logical outputs Y₁ and Y₂. In particular, the frequency detuning $\mathrm{\Delta }\omega$ between the SGDBR and the VCSEL is considered as the control logic signal C. Here, the output amplitudes $E_{\text{inj}1}$, $E_{\text{inj}2}$ and $E_{\text{inj}3}$ are changed with $\mathrm{\Delta }\omega$. Simultaneously, the bias current μ₀ of the SGDBR is varied with the change of these output amplitudes. As a result, $\mathrm{\Delta }\omega$ is further varied with the change of μ₀. We consider μ₀ as square wave, which the low and high levels are set as μ₀₁ and μ₀₂, respectively. Under ${\mu }_0={\mu }_{01}$, the low levels of $\mathrm{\Delta }\omega$ and C are $\mathrm{\Delta }{\omega }_1$ and C₁, respectively. When ${\mu }_0={\mu }_{02}$, the high levels of them are $\mathrm{\Delta }{\omega }_2$ and C₂, respectively. Meanwhile, μ₀₁ and μ₀₁ are varied with the low and high levels of three input signals (I₁, I₂ and I₃), respectively. If the control signal C has the data-selection logic relation with the three signals I₁, I₂ and I₃, it is possible that $Y_1=I_1{\overline{I}}_3+I_2{I}_3$ and $Y_2=I_1{\overline{I}}_3+I_2{I}_3$. However, it is very difficult that the data-selection logic operation that $C=I_1{\overline{I}}_3+I_2{I}_3$ is directly realized since that the C only depends on the injection current μ₀. Tosolve this problem, we propose a scheme to indirectly implement the data-selection operation as follows. The amplitude $E_{\text{inj}1}$ of one beam of light from the FBS₄ is converted into the current signals i₁ by the photo-detector 1 (PD₁). The noise in it from the PD₁ is filtered by the low pass Bessel filter 1 (LPBF₁). The i₁ is amplified by the electric amplifier 1 (EAM₁). The current signals i₂ and i₃ converted by the $E_{\text{inj}2}$ and $E_{\text{inj}3}$, respectively, are processed in the same way. The i₁, i₂ and i₃, in turn, are encoded into three electric logic inputs of the electronic data selector (EDS) such as $i_1^{\prime }$, $i_2^{\prime }$ and $i_3^{\prime }$. The logic sets of the signals $i_1^{\prime }$, $i_2^{\prime }$ and $i_3^{\prime }$ are synchronized with those of the signals I₁, I₂ and I₃. The output of the EDS is considered as μ₀, which is the injection current of the SGDBR. The μ₀ is encoded into the logic output Y₀of the EDS. Here, $Y_0=0$ is encoded in the low-level current μ₀₁, $Y_0=1$ is encoded in the high-level current μ₀₂. Using the EDS, we obtain $Y_0=i_1^{\prime }{\overline{i^{\prime }}}_3+i_2^{\prime }{i}_3^{\prime }$. If $Y_0=0$, ${\mu }_0={\mu }_{01}$, we obtain $\mathrm{\Delta }\omega =\mathrm{\Delta }{\omega }_1$ and $C=C_1=0$; when $Y_0=1$, ${\mu }_0={\mu }_{02}$, we have $\mathrm{\Delta }\omega =\mathrm{\Delta }{\omega }_2$ and $C=C_2=1$. These show that C is logically synchronized with Y₀. Thus, we further obtain $C=I_1{\overline{I}}_3+I_2{I}_3$ when the logic sets of I₁, I₂ and I₃ are synchronized with the those of $i_1^{\prime }$, $i_2^{\prime }$ and $i_3^{\prime }$. In the following, we elaborate the realization of two parallel data-selection computing in detail.

Based on the spin-flip model of VCSEEL presented by Miguel et al [32], the rate equations for the optically injected VCSEL are modified as [33]:

Table 1. Numerical values for optical chaotic data-selection logic operation [27].

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3. Results and discussions

From Fig. 2, it is observed that the output x-PC is chaotic state when E_inj is between 0 and 0.06, or 1.42 and 1.7, or 1.74 and 3 under $\mathrm{\Delta }\omega =0$ GHz; the output y-PC appears chaotic state while E_inj ranges from 0 to 0.32, or from 1.36 to 3. Under $\mathrm{\Delta }\omega =-80$ GHz, the x-PC is chaotic state when E_inj varies from 0.46 to 3, and if E_inj is between 0 and 3, the y-PC is chaotic state. To determine the value of E_inj that is encoded into logical inputs, for $\mathrm{\Delta }\omega =0$ GHz and $-80$ GHz, we calculate the bistability evolutions of the two output PCs with E_inj, as shown in Fig. 3. From this figure, one sees that under $\mathrm{\Delta }\omega =0$ GHz, the bistability-loops of the x-PC and y-PC locate in the space of E_inj between 1.42 to 1.64, where two output PCs are chaotic states. But for $\mathrm{\Delta }\omega =-80$ GHz, the bistability-loops occur at E_inj that varies from 0 to 0.174.

 

Fig. 2 Maps of nonlinear dynamic behavior of the optically VCSEL evolution in the parameter space of E_inj and Δω. Here, CO: chaotic state; QP: quasi-periodic oscillation; P₁: period-one oscillation; P₂: period-two oscillation.

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Fig. 3 For Δω = 0 GHz (a) and −80 GHz (b), the bistability evolutions of the x-PC and the y-PC with the amplitude of the injection field. Here, $I{N}_x=E_x^2$; $I{N}_y=E_y^2$; the red-solid line: the x-PC; the black-solid line: the y-PC; the arrows indicate the four-level signals used to encode the logic inputs (see texts in details).

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We suppose that E_inj equals to the sum of three square waves, i.e., E_inj = $E_{\text{inj}1}$ + $E_{\text{inj}2}$ + $E_{\text{inj}3}$, where $E_{\text{inj}1}$, $E_{\text{inj}2}$ are encoded into logic inputs I₁ and I₂, respectively; $E_{\text{inj}3}$ is used to encode into clock signal I₃. Since logical input can be either 0 or 1, there exist eight distinct sets: (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1). We can encode the eight logic inputs with four-level signals E_injI, E_injII, E_injIII and E_injIV, where E_injI (E_injII - $\mathrm{\Delta }{E}_{\text{inj}}$) represents the set (0,0,0); E_injII denotes the sets (0,0,1), (0,1,0) and (1,0,0); E_injIV (E_injII + $\mathrm{\Delta }{E}_{\text{inj}}$) indicates the sets (0,1,1), (1,0,1) and (1,1,0); E_injvi (E_injII + $2\mathrm{\Delta }{E}_{\text{inj}}$) shows the set (1,1,1). The four-level signal is constant during a bit duration T. Here, T is set to 100 ps or 67 ps, correspondingly, the rate of the chaotic data-selection can be about 10 Gb/s or 15 Gb/s. Since that under $\mathrm{\Delta }\omega =0$ GHz and $-80$ GHz, the two output PCs exhibit chaotic states in the parameter place of E_inj from 1.42 to 1.7 (see Fig. 2), we take $E_{\text{injI}}=1.44$, $E_{\text{injII}}=1.50$, $E_{\text{injIII}}=1.56$ and $E_{\text{injIV}}=1.62$ as the four-level signals (see Fig. 3). Here, when $E_{\text{inj}1}$, $E_{\text{inj}2}$and $E_{\text{inj}3}$ are equal to 0.48, I₁, I₂ and I₃ are considered as 0; if $E_{\text{inj}1}$, $E_{\text{inj}2}$ and $E_{\text{inj}3}$ are equal to 0.54, I₁, I₂ and I₃ become 1. In addition, when $\mathrm{\Delta }\omega =0$ GHz, C = 1; C = 0 under $\mathrm{\Delta }\omega =-80$ GHz. To encode the logical output, we use the threshold mechanism to determine two logic outputs from the VCSEL. The threshold mechanism can be established when the conversion between the output x-PC and y-PC from the VCSEL is induced by the variation of the frequency detuning $\mathrm{\Delta }\omega$ or the bias current μ₀ between the low-level and high-level. The threshold mechanism is further explained as follows. Suppose that the total sampling time t is equal to L times the bit duration T, i.e., $t=LT$. The number of sampling times in each T is defined as M, and equal to $T/h$, where h is the time iteration step. The mean value of the output x-PC and y-PC in the ith T (i=0, 1, 2, …, L, the same below) are defined as $A_{x\left(i\right)}$ and $A_{y\left(i\right)}$, respectively, which are expressed as

For another case, under C = 0, suppose that the x-PC is suppressed and the y-PC is dominant in the output of the VCSEL, we obtain

For C = 1, if the output of the VCSEL is governed by the x-PC, and its output y-PC is suppressed, the minimum value of $A_{\mathrm{x}\left(\mathrm{i}\right)}$ and maximum value of $A_{\mathrm{y}\left(\mathrm{i}\right)}$ are, respectively, computed by

From Eqs. (13)-(16), we obtain the thresholds of the two PCs as follows,

More significantly, in the eight distinct sets of three input signals I₁, I₂ and I₃, suppose that the number of the mth input set is l_m (m=1, 2, …, 8, the same below). Correspondingly, there are the response logic outputs with the number of l_m in the output x-PC and y-PC. Therefore, for the mth input set, the minimum and maximum of $A_{\mathrm{x}\left(\mathrm{i}\right)}$ are, respectively, obtained in the output x-PC by

Similar, in the output y-PC, we obtain

Table 2. Combinations of inputs and outputs for chaotic logic selection operations under T = 100 ps.

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Table 3. Combinations of inputs and outputs for chaotic logic selection operations under T = 67 ps.

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Fig. 4 For T = 100 ps and T = 67 ps, the implementations of two parallel optical chaotic data-selection computing. Left column: T = 100 ps; right column: T = 67 ps. (a) and (e) show the temporal traces of Δω and E_inj; the blue-dashline: the frequency detuning Δω; the red-solid line: the four-level signals E_inj; (b) and (f) present the logic data-selection operation between C and the three signals including I₁, I₂ and I₃, where the green, yellow and purple solid lines represent I₁, I₂ and I₃, in turn, and the black-solid line represents the control logic signal C; (c) and (g) show the temporal trace of the output x-PC and the corresponding Y₁; (d) and (h) display the temporal trace of the output y-PC and the corresponding Y₂.

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In particular, to obtain two identical logical output response encoded in the output x-PC and y-PC, the threshold judgement rule for the output x-PC is opposite to that for the output y-PC, due to the conversion between the output x-PC and y-PC. Based on the above considerations, for the mth input set, if $B_{\mathrm{x}min}^m$ > $A_{\text{xth}}^1$ or $A_{\text{xth}}^2$, $Y_1=0$; when $B_{\mathrm{x}max}^m$ < $A_{\text{xth}}^1$ or $A_{\text{xth}}^2$, $Y_1=1$. While $B_{\mathrm{y}max}^m$ < $A_{\text{yth}}^1$ or $A_{\text{yth}}^2$, $Y_2=0$; under $B_{\mathrm{y}min}^m$ > $A_{\text{yth}}^1$ or $A_{\text{yth}}^2$, $Y_2=1$. In our simulations, $L=1280$, h = 1 ps, n₀ = n₁ = 640, l_m = 160. According to the above-mentioned encoding principle of the logic inputs and outputs, we present the implementation of optical chaotic logic selection operation, as shown in Fig. 4, where the amplitude of the injected light field varies with fast four-level signals. From Figs. 4(b) and 4(f), it is found that $C=I_1{\overline{I}}_3+I_2{I}_3$ under $C=i_1^{\prime }{\overline{i^{\prime }}}_3+i_2^{\prime }{i}_3^{\prime }$. Table 2 shows the combination of the logical inputs, clock signal, control signal and logical outputs under T = 100 ps. As further shown in Fig. 4, the x-PC is dominant and the y-PC is suppressed in the output of the VCSEL under C = 0. But for C = 1, the x-PC is suppressed and the y-PC is dominant. Under the condition, according to Eqs. (5)-(12), we obtain the thresholds as follows: $A_{\text{xth}}^1$ = 0.5653 and $A_{\text{yth}}^1$ = 0.6821 under T = 100 ps; $A_{\text{xth}}^1$ = 0.8439 and $A_{\text{yth}}^1$ = 0.6004 when T = 67 ps. From Table 2 and Figs. 4(c) and 4(d), it is further seen that under T = 100 ps, if (I₁,I₂,I₃) = (0,0,0), $B_{\mathrm{x}min}^1$ = 0.5788 and $B_{\mathrm{y}max}^1$ = 0.5248; under (I₁,I₂,I₃) = (0,0,1), $B_{\mathrm{x}min}^2$ = 0.6992 and $B_{\mathrm{y}max}^2$ = 0.5062; when (I₁,I₂,I₃) = (0,1,0), $B_{\mathrm{x}min}^3$ = 0.6873 and $B_{\mathrm{y}max}^3$ = 0.5290; while (I₁,I₂,I₃) = (1,0,1), $B_{\mathrm{x}min}^6$ = 0.7864 and $B_{\mathrm{y}max}^6$ = 0.5215. It is obtained that Y₁ = 0 and Y₂ = 0 since $B_{\mathrm{x}min}^m$ > $A_{\text{xth}}^1$ and $B_{\mathrm{y}max}^m$ < $A_{\text{yth}}^1$ (m = 1, 2, 3, 6). In addition, if (I₁,I₂,I₃) = (0,1,1), $B_{\mathrm{x}max}^4$ and $B_{\mathrm{y}min}^4$ are found to be 0.5379 and 0.8396, respectively. Under (I₁,I₂,I₃) = (1,0,0), $B_{\mathrm{x}max}^5$ and $B_{\mathrm{y}min}^5$ are of 0.5517 and 0.8352; when (I₁,I₂,I₃) = (1,1,0), $B_{\mathrm{x}max}^7$ and $B_{\mathrm{y}min}^7$ becomes 0.5214 and 0.8614; while (I₁,I₂,I₃) = (1,1,1), $B_{\mathrm{x}max}^8$ and $B_{\mathrm{y}min}^8$ are of 0.4660 and 0.8792, respectively. Thus, we obtain $Y_1=1$ and $Y_2=1$, owing to the case that $B_{\mathrm{x}max}^m$ < $A_{\text{xth}}^1$ and $B_{\mathrm{y}min}^m$ > $A_{\text{yth}}^1$ (m = 4, 5, 7, 8). It is concluded that $Y_1=I_1{\overline{I}}_3+I_2{I}_3$ and $Y_2=I_1{\overline{I}}_3+I_2{I}_3$, showing that two parallel optical chaotic data-selection operations can be implemented. Under T = 67 ps, Table 3 presents the combinations of inputs and outputs for chaotic logic selection operation. The evolutions of the logic data-selection operation are displayed in the right column of Fig. 4. From Table 3 and Figs. 4(e)-4(h), the evolutions of the logic data-selection operation have similar behaviors with those under T = 100 ps. However, there exit some error bits in the output of Y₁

owing to the faster chaotic polarization fluctuation of the response output for the x-PC caused by the shorter injected bit duration. Under the condition, using the threshold mechanism provided in Eqs. (5)-(12), the partial logic outputs are wrongly encoded in the output x-PC. As a result, the case that $Y_1=I_1{\overline{I}}_3+I_2{I}_3$ cannot be rightly realized. By comparison, the data-selection computing that $Y_2=I_1{\overline{I}}_3+I_2{I}_3$ can be rightly implemented. In order to further evaluate the output performance of digital chaotic data-selection under T = 100 ps and 67 ps, we further discuss the success probability in detail as follows.

 

Fig. 5 Mappings of the evolutions of the success probability P for the chaotic logic outputs Y₁ and Y₂ in the parameters of T and K_x (K_y). (a): P of Y₁; (b): P of Y₂.

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Fig. 6 The success probabilities P for the chaotic logic outputs Y₁ and Y₂ under the different noise conditions. (a): the success probabilities of Y₁; (b): the success probabilities of Y₂.

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It is noted that the data-selection logic computing depends on some key parameters of the system such as the bit duration, the injection strength and the noise strength. In other words, these parameters seriously influence the reliability of the data-selection logic operation. For this purpose, we introduce the success probability P to describe the reliability. It is defined as the ratio between the number of the correct bits and that of total bits of the chaotic logic output. Firstly, we calculate the evolutions of the success probability in the parameter space of K_x and T, as well as K_y and T when K_x = K_y. The results are displayed in Fig. 5. From Fig. 5(a), one sees that under T = 100 ps, the output Y₁ shows error-free bits when K_x and K_y increase from 19.6 ns${ }^{-1}$ to 50 ns${ }^{-1}$. With the further increase of K_x and K_y, the shorter bit duration of Y₁ with error-free bits can be obtained. For example, there are no error bits in the output Y₁ when K_x and K_y are more than 50 ns${ }^{-1}$. As seen from Fig. 5(b), when K_x and K_y are between 16 ns${ }^{-1}$ and 37.2 ns${ }^{-1}$, the output Y₂ appears error-free under T = 100 ps. But for T = 67 ps, the output Y₂ with error-free occurs in a narrow region, where K_x and K_y range from 20 ns${ }^{-1}$ to 23.6 ns${ }^{-1}$.

To observe the influence of the noise strength ${\beta }_{\text{sp}}$ on the success probability, we calculate the dependence of the success probability on the noise strength ${\beta }_{\text{sp}}$. From Fig. 6(a), it is found that the P of the Y₁ is equal to 1 when ${\beta }_{\text{sp}}$ < 3.2 × 10⁹. As shown in Fig. 6(b), the P of the Y₂ keeps to be 1 when ${\beta }_{\text{sp}}$ < 304 × 10⁹. These show that no error bits occur in the Y₁ and Y₂ under high noise strength. Therefore, two parallel chaotic data-selection computing have excellent anti-interference ability.

4. Conclusions

In conclusion, based on the chaotic polarization in an optically injected VCSEL, we propose a novel scheme for the realization of two parallel optical chaotic data-selection computing in which the bit duration is picosecond magnitude, controlling indirectly the logic data-selection relation between the frequency detuning and three signals including one optical clock signal and two optical input ones. Moreover, the success probabilities of two parallel chaotic data-selection operation are further explored in the parameter spaces of the injection strength and the bit duration. It is found that the response of the correct logic outputs encoded in the output x-PC and y-PC is short as 100 ps bit time, and that of the correct logic output encoded in the output y-PC may be short as 67 ps by the optimization of the injection strength. Finally, the success probabilities for two data-selection computing have strong robust to the noise strength. An attractive advantage of the VCSEL-based data-selection operation for practical applications is the very short bit time needed to produce the correct operation with probability equal to 1 (in our simulations, about 67 ps - 100 ps). In addition, the chaotic data-selection computing in an optically VCSEL has potential applications in optical chaotic secure communication and optical chaos computing architecture where noise is unavoidable.