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Abstract
In this paper a novel opto-electronic Track-and-Hold Amplifier (OE-THA) is presented. The OE-THA can be used as a sampler in a photonic analog-to-digital-converter (ADC). It is fabricated in a silicon photonic 250 nm SiGe BiCMOS technology to allow for monolithic integration of photonic and electronic components. The OE-THA chip exhibits a small signal bandwidth of over 65 GHz, a total harmonic distortion below −34 dB up to 75 GHz and a signal-to-noise and distortion ratio (SINAD) of over 35 dB (5.5 effective bits, ENOB) up to 45 GHz. The measured resolution bandwidth products result in a corresponding equivalent jitter of below 80 fs rms from 20 to 70 GHz. The best equivalent jitter is achieved at 41 GHz with a value of 55.8 fs rms. This is enabled by using a low-jitter optical pulse train, generated by a Mode-Locked-Laser (MLL), as an optical sampling clock. The circuit integrates all optical and electronic components besides the MLL. It draws 110 mA operated from a supply voltage of −4.6 V and occupies a silicon area of only 0.59 mm2.
© 2021 Optical Society of America under the terms of the OSA Open Access Publishing Agreement
1. Introduction
In digital communication systems as well as high-end measurement equipment broadband ADCs play an important role. Often sampling rate, effective resolution, and bandwidth of the data converters limit the overall performance of the communication or measurement system. State-of-the-art ultra-broadband ADCs implemented in CMOS technologies are mostly based on time-interleaving (TI) and use large numbers of low-power, low-speed sub-ADCs in parallel. In this way very high sampling rates of more than 100 GS/s and moderate power dissipation have been achieved. E.g. the TI ADC presented in [1] uses 64 sub-ADCs and achieves a conversion rate of 90 GS/s with an analog input bandwidth of around 20 GHz. However, at high input frequencies above a few GHz, the ADC precision is fundamentally limited by the clock jitter or more precisely the product of aperture clock jitter and input signal frequency [2]. This effect is independent of the type of sampler or ADC architecture used and is only caused by the timing uncertainty of the sampling due to electronic clock jitter. Compared to electronic clocks the envelope of an optical pulse train generated by a mode-locked laser (MLL) can achieve an RMS timing-jitter in the attosecond region [3,4]. This has led to research into photonic samplers and ADCs where the sampling clock is provided by a low-jitter MLL [5–8].
Up till now, different techniques for samplers using an MLL as sampling clock have been proposed [5]. A popular approach is to use an electro-optic modulator such as a Mach-Zehnder modulator (MZM) whereby the electrical input signal modulates the intensity of the MLL pulse train [6,9]. Others have used photo-conductive switches which are illuminated by MLL pulses [10]. Several groups also reported diode bridge samplers which were clocked with MLL pulse trains [11,12]. In [13] the pulse train of an MLL is converted to an electrical signal by means of a photodetector and multiplied with the analog input signal in the electronic domain.
Previously we proposed a novel type of MLL-based sampler: The opto-electronic switched-emitter-follower (OE-SEF) [14]. In the OE-SEF the optical pulse train from an MLL is converted to an electrical clock signal which is then used to control a switched-emitter-follower (SEF) sampler. The SEF architecture is chosen, because it has shown the best performance in terms of bandwidth and resolution compared to other electronic samplers in silicon technologies [15–17]. In [7] the OE-SEF was analyzed and compared to MZM-based sampling theoretically and by means of simulation. It was shown that the OE-SEF provides a higher bandwidth than MZM-based samplers in state-of-the-art silicon photonic technologies and achieves a high linearity without need for digital post processing. Hence the OE-SEF is excellently suited as a sampler for future photonic TI ADCs in silicon photonics technology.
In this paper the implementation and experimental validation of an OE-SEF sampler in silicon photonics technology is reported for the first time. The OE-SEF chip was fabricated in a silicon photonic 250 nm SiGe BiCMOS technology [18] monolithically integrating optical and electronic components on a single chip. The presented results are an important step towards ultrabroadband photonic analog-to-digital converters in silicon photonics technology.
The paper is organized as follows: In section 2 the individual circuit components and their design are explained on schematic level. Section 3 gives an insight into the chip layout and describes the used small- and large-signal measurement setup. The measurement results are presented in detail in section 4 and section 5 concludes the paper.
2. Circuit description
A block diagram of the circuit is shown in Fig. 1. It can be divided into six components: the photonic frontend (grating coupler, rib waveguide with taper, waveguide-integrated Germanium photodetector, and transimpedance amplifier), 50 Ω analog input stage (InBuf), main amplifier (MA), switched-emitter-follower (SEF), output buffer (Out), and 50 Ω test buffer (Test). A simplified schematic of the 50 Ω analog input buffer and core circuit comprising the MA and the SEF is shown in Fig. 2. The implemented THA is fully differential and can thus make use of high common mode rejection and good suppression of even order harmonics.
Fig. 1. Block diagram showing the individual circuit components of the silicon photonic chip. Photonic components: grating coupler (GC), taper, optical waveguides, PIN photodiode (PD), transimpedance amplifier (TIA). Electrical components: 50 Ω input buffer (InBuf), main amplifier (MA), switched-emitter-follower (SEF), output buffer (Out) and 50 Ω test buffer (Test).
Fig. 2. Simplified schematic of the 50 Ω input stage, main amplifier and switched-emitter-follower, including the pedestal compensation.
2.1 Input stage, main amplifier and feedthrough attenuation
The input stage is implemented as an emitter-follower buffer with a 50 Ω resistor from $v_{IN}$ to $V_{CC}$ for power matching, see Fig. 2. A second emitter-follower is used to drop the input voltage by another $V_{\textrm {be,on}}$. This gives enough voltage headroom for the main amplifier (MA), that is implemented as a differential amplifier. To increase the bandwidth a differential cascode amplifier (Q5 to Q8), capacitive peaking $C_E$, and resistive degeneration $R_E$ are used. Resistive degeneration also improves the linearity of the amplifier. To compensate for losses in the following stages, the gain is designed to be slightly higher than one.
Additionally, an active feedthrough attenuation network, see Fig. 3(a), with comparable functionality to the one presented in [19] is introduced. In principle, the feedthrough attenuation network is a copy of the MA, but the output is reversely connected to the nodes x+ and x-. During the hold-mode the currents in the collector resistors $R_C$ are therefore compensated and a very high hold-mode isolation results.
Fig. 3. (a) Active feedthrough attenuation circuit, (b) feed forward capacitance $C_{\textrm {ff}}$ (4-transistor network) used to compensate the base-emitter capacitance, (c) simplified schematic of the transimpedance amplifier (TIA) converting the optical pulse train to an electrical signal.
2.2 THA core: switched-emitter-follower (SEF)
The core of the circuit is the SEF-Sampler (Transistors Q9-Q14, Fig. 2). In the track-mode transistors Q11/Q13 are switched on and the current $I_{\textrm {SEF}}$ is completely flowing through Q9/Q10. By biasing Q9/Q10 properly, they act as a high bandwidth emitter-follower buffer. The voltage at the hold capacitor $C_H$ follows the input. During the hold-mode Q11/Q13 are off and Q12/14 are on. Hence, no current flows through Q9/Q10. $I_{\textrm {SEF}}$ is instead drawn through the collector resistors $R_C$ of the main amplifier, leading to a voltage drop at nodes x+/x- of $\left [(I_{\textrm {SEF}}+ I_{\textrm {diff2}}/2)\cdot R_C\right ]$. This voltage drop is chosen large enough to bring Q9/Q10 safely into the cut-off region. Thus the nodes x+ and x- are disconnected from the hold capacitors $C_H$ and the circuit is in hold mode.
The parasitic base-emitter capacitances of Q9/Q10 lead to a feedthrough of high frequency input signals to the hold capacitors and thus the output during the hold-mode. To reduce the feedthrough further, cross coupled feed forward capacitors $C_{\textrm {ff}}$ can be used. They must have the same value as the base-emitter capacitances of Q9/Q10. A well-known technology independent technique, that is also used in this design, is a four transistor network shown in Fig. 3(b) [20]. The transistors $Q_p$ in Fig. 2 are implemented in open emitter configuration. Their base-collector capacitance ($c_{bc}$) is used to compensate the charge injection onto the hold-capacitor during clock-switching by the base-collector capacitance of the switching transistors (Q11-Q14) [21].
2.3 Output buffer and 50 Ω test buffer
The output buffer is implemented as another emitter follower stage. Its main purpose is to provide a high impedance to the hold capacitor node and shielding it from the high current 50 Ω test buffer. During the hold-mode the base current of the output buffer discharges the hold capacitor, leading to a voltage droop over time. To keep the base current low the emitter-size is chosen as small as possible. Simulations have shown a very low base current. Therefore, base current compensation techniques as shown in [19] are not applied, since they tend to reduce the bandwidth. For a sampling clock rate in the GHz-range and hence shorter hold phase, the discharging current will not be an issue in this design. The 50 Ω test buffer is implemented similar to the main amplifier as a cascode differential amplifier with emitter degeneration, but without capacitive peaking. To achieve power matching at the output of the test buffer collector resistors are chosen to be $50\,\Omega$.
2.4 Transimpedance amplifier
As explained in the beginning a single ended TIA, depicted in Fig. 3(c), converts the optical MLL pulse train to an electrical clock signal. It is designed as a common base TIA with a transimpedance of $R_1=100\,\Omega$ and followed by an emitter-follower buffer (Q22). The output of the buffer is connected to the bases of Q12/Q14 in Fig. 2 (node H). The bases of Q11/Q13 in Fig. 2 (node T) are set to a constant voltage, that can be controlled externally through the voltage $V_{\textrm{ext}\_\textrm{bias}}$ (Fig. 3(c)). Therefore, the clock signal in this design is pseudo differential. When no light is incident onto the waveguide-integrated germanium photodiode the TIA is biased such that the voltage at node H is higher than the voltage at node T and the THA operates in the hold-mode.
3. Layout and measurement setup
3.1 Layout
The chip was designed and fabricated in a silicon photonic 250 nm BiCMOS process with a transit frequency of $f_T = 220\,\textrm {GHz}$ (SG25H5_EPIC [18]) and occupies an area of only 0.59 mm$^{2}$. A micro-photograph is shown in Fig. 4(a). Both, input and output high-frequency pads are designed in GSSG configuration. The supply voltage and DC biasing pads are wire-bonded to a PCB. To couple the light into the chip a cleaved fiber is placed above a grating coupler (GC, see Fig. 4(a)) in an angle of approximately 10 degrees. Since the circuit is differential the layout is kept as symmetric as possible.
Fig. 4. (a) Micro-photograph of the fabricated chip. Dashed squares: GC (Grating Coupler), TIA (Transimpedance-Amplifier). (b) Transient measurement setup for input frequencies above 50 GHz. From 0-50 GHz the signal generator output is directly connected to the THA input
3.2 Measurement setup
S-parameter (small-signal) and transient (large-signal) measurements are carried out. The s-parameter measurements are performed using GSSG HF-Probes and a 70 GHz vector network analyzer (Anritsu VNA MS4647b). All cables and probes are calibrated out.
The setup used for transient measurements is shown in Fig. 4(b). For frequencies below 50 GHz the output of the signal generator (Agilent 83650L) is directly connected to the positive THA input using a GSSG high-frequency probe. For frequencies above 50 GHz the signal generator output is amplified with a microwave amplifier (Hewlett Packard 8349B) and quadrupled by a Millimeter-Wave Source Module (Agilent 83557A). Then, a GSG waveguide-probe is used for the electrical connection at the input. The sampling clock-signal is generated by a Menhir-1550 MLL with a repetition rate of 250 MHz [22]. A tunable optical filter (Finisar Waveshaper 4000A) introduces a dispersion of 6 ps/nm before the light is vertically coupled into the chip by means of a grating coupler. The electrical output is captured with a real-time oscilloscope (Keysight UXR0702A) and a spectrum analyzer (Anritsu MS2760A). The frequency span of the spectrum analyzer corresponds to the first Nyqist zone of 0-125 MHz and is captured with 4000 points. The resolution bandwidth and video bandwidth is set to 1 kHz, which would correspond to an effective observation time of 1 ms if a time series had been taken instead. Due to sub-sampling all frequencies, including fundamental, harmonics and spurs, are mixed/mirrored down to this frequency band.
The spectrum analyzer data is used to calculate the signal-to-noise and distortion ratio (SINAD/SNDR) from which the effective resolution (equivalent number of bits, ENOB) can be calculated. Timing-jitter effects the SNR of a sinusoidal input signal as given by (1), where $f_{\textrm {sig}}$ is the analog input frequency and $\sigma _{\textrm {ji}}$ the rms jitter. Equation (1) is derived in [23] neglecting amplitude noise. Rearranging (1) by $\sigma _{\textrm {ji}}$ and inserting the measured SINAD values the equivalent jitter can be calculated. The equivalent jitter gives an upper boundary. The clock jitter is always equal or lower than the equivalent jitter, especially since other noise effects also degrade the SINAD and thus ENOB.
4. Measurement results
4.1 Small- and large-signal bandwidth
Figure 5(a) shows the single-ended s-parameter measurement results. The circuit is successively set to track-mode and to hold-mode through external biasing. In track-mode operation s21 is found at −5 dB and stays flat within approximately 2 GHz. Then it slowly starts to drop, showing a 3 dB small signal bandwidth of 65 GHz. At 50 GHz a peaking is clearly seen. It results from the designed capacitive peaking in the main amplifier and additionally from the hold capacitance, that represents a capacitive load to the switched-emitter-follower stage, thus causing bandwidth peaking [24]. The circuit provides a small overall gain of 1 dB as for a single-ended measurement −6 dB is expected for a unity gain amplifier.
Hold-mode feedthrough stays below −30 dB up till 40 GHz, forms a peak of −21 dB at 50 GHz and drops again for higher frequencies. The observed peak at 50 GHz is much more pronounced compared to simulations. More care has to be taken on the attenuation and feedthrough compensation circuits in future designs, since other implementations without an explicit attenuation network have shown comparable/better hold-mode isolation [15]. Most likely it results from a current mismatch between $I_{\textrm {diff}}$ (Fig. 2) and $I_{\textrm {diff2}}$ (Fig. 3(a)).
Fig. 5. (a) Single-ended s-parameter measurements of THA, while externally biased successively in the hold-mode (purple graph) and in the track-mode (yellow graph), (b) normalized power during track-and-hold operation calculated from spectrum-analyzer data.
The normalized power of the fundamental input frequency, mirrored to the first Nyquist zone, is plotted in Fig. 5(b). Setting the reference to 5 GHz, to exclude the self-heating effect in bipolar transistors, a 3 dB drop can be observed at 43 GHz and a 5 dB drop at 50 GHz. Cable and rf-probe losses of over 2 dB at 50 GHz are not de-embedded, such that a large-signal bandwidth of approximately 50 GHz is found. The discontinuity seen at 50 GHz results from the previously explained change in the measurement setup for frequencies above 50 GHz, see Fig. 4(b). The power after the microwave amplifier can be measured, but the power after the wave source module and waveguide probe is unknown and could only be estimated from the spectrum analyzer data. Unfortunately, a presumably not circuit related power fluctuation in the region between 50 GHz and 60 GHz complicates the estimation, see Fig. 5(b).
4.2 Transient measurements
Figure 6(a) shows the single-ended output of the THA, during operation, captured by a real-time oscilloscope. The track- and the hold-phase can clearly be distinguished. Due to the short optical pulses the track-phase becomes very short. The low sampling rate of 250 MHz (repetition rate of the MLL) leads to a comparably long hold-phase during which the hold-capacitor gets slowly discharged. On one hand the effect of capacitor discharge (droop) on the output signal is reduced, considering the differential signal. On the other hand, increasing the repetition rate to 500 MHz or higher, e.g. by means of a rate multiplier, would already significantly reduce this effect.
The spectrum analyzer data is used to calculate multiple figures of merit. Those are: the signal-to-noise and distortion ratio (SINAD or SNDR), the total harmonic distortion (THD), the spurious free dynamic range (SFDR) and the signal-to-noise ratio (SNR). Two example spectrums are shown in Fig. 6(b).
Fig. 6. (a) Single-ended real-time measurement data for different input frequencies, (b) normalized spectrum analyzer data and important figures of merit for $P_{\textrm {in}}=$ −10 dBm, $f_{\textrm {in}}=$ 19.27 GHz/43.27 GHz. Resolution and video bandwidth are set to 1 kHz.
Fig. 7(a) shows the achieved ENOB as a function of SINAD on the left ordinate and the corresponding SINAD on the right ordinate versus the input frequency on the abscissa for varying input powers. The circuit maintains an ENOB of over 5.5 Bit SINAD up to approximately 45 GHz and depending on the input power over 5 Bit SINAD up to 65 GHz. It can be seen that the equivalent jitter stays in a region between 80 to 55 fs up to over 65 GHz. The best equivalent jitter is achieved at 41 GHz with 55.8 fs rms at −5 dBm input power.
Fig. 7. (a) ENOB(SINAD) vs. frequency for varying input powers. The dashed lines show the 55 fs, 80 fs and 100 fs equivalent jitter limit respectively. (b) ENOB(THD) vs. frequency for varying input powers.
For frequencies below 15 GHz the achieved ENOB is mostly determined by the total harmonic distortion, see Fig. 7(b). It shows the THD of the circuit calculated from the first five harmonics on the right ordinate versus the input frequency. Some authors also calculate ENOB as a function of THD, which can be seen on the left ordinate. Naturally, increasing the input power leads to a lower resolution (higher THD), since the circuit is driven into nonlinear operation regions. The best results are obtained for −10 dBm input power leading to an ENOB of 6.2 Bit THD up to 50 GHz and over 5.5 Bit THD up to 75 GHz. But, a low power input signal reduces the SNR, which is why the ENOB(SINAD) graph (Fig. 7(a)) should be used to find a trade-off between nonlinearity effects and overall noise.
4.3 Discussion
Pre-characterizations of the circuit have shown, that the OE-THA operates without compression within an input voltage range of $0.8\,V_{\textrm {pp}}$ (differential). Therefore, the highest input power applied to one of the two inputs is −4 dBm ($0.4\,V_{\textrm {pp}}$ in a 50 $\Omega$ system). To characterize the TIA stage, which showed 30 GHz bandwidth in simulation, the chip is tested with a CW laser and an intensity modulator. For full switching from hold- to track-mode a CW laser power of at least 10 dBm is needed due to low transimpedance gain ($100\Omega$) and grating coupler losses (more than 5 dB). Switching behavior is seen up to 18 GHz, where the used intensity modulator has its bandwidth limit.
The Menhir-1550 MLL used has an average power of 18 dBm and optical spectrum analyzer (OSA) measurements show a 3 dB optical bandwidth of 10 nm. Assuming a $\operatorname {sech}^{2}$ pulse-shape and that the pulse is transform limited, as stated by the manufacturer, the full width half maximum (FWHM) pulse width in time domain is estimated to 250 fs. Applying the optical pulse train directly to the chip does not show good performance in terms of switching, thus pulse-shaping is necessary for the OE-THA. As shown in Fig. 4(b) a tunable optical processor (Waveshaper 4000A) is used to introduce a dispersion. The results improve significantly with dispersion settings ranging from 1 ps/nm to 10 ps/nm, where 6 ps/nm is empirically determined to being the optimum. Although group velocity dispersion (GVD) in on-chip silicon waveguides can be in the range of several 1000 ps/nm/km [25] it should not play a role here, since the total waveguide length is only $\approx500\;\mu \textrm {m}$. Based on expected values from the literature and simulations GCs show a 1 dB bandwidth of over 10 nm and do not introduce a significant dispersion (5·10−4 ps/nm simulated) as well [26]. Therefore, the dispersion introduced by the waveshaper does not compensate on-chip dispersion, but is used to broaden the pulse in time domain. 6 ps/nm dispersion increases the temporal FWHM of a gaussian-shaped pulse from 250 fs to approximately 84 ps. Peak-power is reduced accordingly. Since the pulse is broadened in time domain its bandwidth is reduced for the detection electronics. It is assumed that broader pulses are needed to allow the SEF to have sufficient time for tracking.
Performance degradation could also result from high peak-power that could saturate the photodetector or secondary effects like mechanical vibrations of the single mode fiber mounted above the GC and spectral distortions caused by standing waves, which are generated by GC reflections. Amplitude noise will also degrade the performance, but compared to the MZM-sampling approach it does not directly transform to noise on the signal, but rather decreases the tracking period and reduces the clock-signal slope. This and other effects have to be further analyzed empirically and analytically.
5. Conclusion and outlook
We present schematic and layout level design and measurement results of a novel opto-electronic sampler: the optically clocked switched-emitter-follower track-and-hold amplifier. It is implemented in an advanced silicon photonic BiCMOS technology monolithically integrating photonic and electronic components. The circuit exhibits a small-signal bandwidth of over 65 GHz and a large signal bandwidth of approximately 50 GHz. An ENOB of over 5.5 Bit SINAD is achieved up to 45 GHz and depending on the input power over 5 Bit SINAD up to 65 GHz. Generally, the corresponding equivalent jitter for frequencies above 20 GHz stays in a range between 80 to 55 fs up to the full bandwidth of 65 GHz, which results in a record resolution if it can be transferred to a complete ADC system [27]. The best equivalent jitter of 55.8 fs rms is found at 41 GHz and could be limited by either the MLL or the rf signal generator. This jitter remains significantly above that of the independently characterized MLL jitter of below 10 fs rms (integrated from 100 Hz to 10 MHz [22]). Hence, there might be a significant contribution from the signal itself, as generated by the rf signal generator. Characterization below this floor would thus require better signal generators such as e.g. frequency synthesizers locked to MLLs [28].
Future work can give attention to further optimizations of the circuit in terms of linearity and noise, as well as to investigate the effects of the degradation of optical pulses in the tiny silicon waveguides (two photon absorption) and saturation effects in the photodetector on the rms timing jitter of the system [29]. The presented circuit can be used in a photonic time-interleaved ADC by e.g. splitting and interleaving the MLL pulse train [29]. Although in this paper the results are shown using a 250 MHz repetition rate MLL, a higher repetition rate MLL can be used without any modifications to the chip.
The comparison to state of the art work is shown in Table 1. In [13] the authors use the same technology but a different architecture compared to the one presented in this paper. While the authors in [13] have tested their circuit with higher sampling rates and achieved a THD of <−33 dB up to 32 GHz, the OE-SEF-THA provides comparable THD over a larger frequency range and a substantially lower power consumption. Additionally, the presented circuit achieves the highest bandwidth and ENOB for input frequencies over 10 GHz among other integrated solutions. As seen in Table 1 MZM-based photonic samplers have shown great results but the performance of on-chip integrated MZM-based samplers lacks behind their discrete counterparts [6]. Furthermore, MZM-based sampling requires digital post processing to compensate for the cosine-shaped transfer characteristic of the MZM [6]. Finally, since the publication of [6] integrated MZMs improved notably, but still today’s best in class all-silicon MZMs achieve bandwidths of maximum 40 GHz [7], whereas the presented optoelectronic SEF-THA achieves 65 GHz with excellent linearity and no need for post processing.
Table 1. Comparison to the state of the art
Funding
Deutsche Forschungsgemeinschaft (403188360, 424608109).
Acknowledgments
The authors acknowledge funding from the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) for the project “Ultra-Wideband Photonically Assisted Analog-to-Digital Converters” (PACE, project no. 403188360) within the priority program SPP2111 and for the project “Ultra-wideband Sampling” (project no. 424608109) within the research unit "Metrology for THz communication" (FOR2863).
Disclosures
The authors declare no conflicts of interest.
Data availability
Design data cannot be made available due to legal restrictions from the foundry. Measurement data may be obtained from the authors upon reasonable request.
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