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Conferences > CLEO_SI > 2023 > SM4G > SM4G.6

An integrated Si3N4 Row Decoder Circuit for Addressable Optical RAM Banks

Stelios Simos, Theodoros Moschos, Chris Vagionas, Theoni Alexoudi, Konstantinos Fotiadis, Dimitrios Chatzitheocharis, Davide Sacchetto, Michael Zervas, and Nikos Pleros

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Abstract

We demonstrate experimentally an integrated Si3N4 photonic 2x4 Row Decoder that utilizes a MRR-based wavelength filtering bank for successfully addressing one out of four RAM rows within an optical RAM bank architecture.

© 2023 The Author(s)

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