Abstract

The complexity of the very large scale integrated circuits can cause great constraints on intrachip and interchip communication capabilities. In comparision, a free-space interconnection network such as a butterfly interconnection has the advantage that it does not require magnification of the input arrays.¹ Further, it may be used to realize all of the logic functions and operations that have already been obtained by using perfect-shuffle.² Herein, we show a novel approach for realizing a 2 × 2 multiplier and then extend the technique for realizing an n-bit parallel-in parallel-out (PIPO) shift register using sequential logic gates.

© 1992 Optical Society of America