Abstract

A cache is a high speed memory located between processors and main memory to fill the speed gap between them. In a loosely coupled parallel computer, each processor has its own cache memory. The processor accesses information from its cache memory, which stores information obtained from the main memory through an interconnection network. A major challenge in this system is to keep the data in all the caches consistent with that in main memory. This is referred to as the cache coherence problem. One solution is to have a bus between the caches, and supply each cache with a controller which listens to the bus and updates the cache whenever a change is made in main memory. This approach is complicated and is limited by the bandwidth of the bus [1], In a tightly coupled parallel computer, the cache memory can be shared by all processors and there is no cache coherence problem. However, with conventional VLSI implementation, only one processor can access the cache memory at a given time and the performance degrades dramatically [2]. We present optical solutions to the above cache problems. We describe an optical bus which updates the multiple caches in loosely coupled parallel computers to eliminate the bandwidth limitation. Optical or optoelectronic cache memory is proposed for shared cache in tightly coupled parallel computers to allow parallel access. We examine potential architectures and devices for both cases.

© 1993 Optical Society of America