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Implementation of a Parallel Ring Interconnect using Smart Pixel Transmitter-Receiver Arrays

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Abstract

Smart pixel systems that utilize a ring architecture to interconnect arrays of optical modulators or emitters have applications in optical memory interconnects, large ATM switches and interconnects between the processors of supercomputers. In this type of system, point to point optical interconnections enable the parallel transfer of arrays of optically encoded data between several device planes organized in a ring topology. One of our primary motivations in developing this architecture is to enable two-dimensional planes of digitally encoded data that is output from a volume optical storage subsystem, to be transferred with high bandwidth to a combination of processors and memories. Many applications utilizing these upcoming high density, high capacity, fast access storage subsystems will combine a number of storage units with multiple heterogenous processing units with high bandwidth, parallel interconnects. We have focused on developing a generic, high bandwidth, free-space parallel interconnect that could be applied to providing interconnections between page-oriented optical memories and both optoelectronic and electronic processors. The advantages of a parallel free-space approach for interconnection of high performance memories are the high spatial bandwidth of the interconnect, similarity of storage and transfer formats, low crosstalk between data channels, electrical isolation and immunity to electrical interference.

© 1997 Optical Society of America

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