Abstract

The combined exploitation of free-space optical interconnections and very large scale integrated (VLSI) electronics has recently allowed the construction of demonstrator systems [1,2] which exhibit on/off chip communication rates at least one order of magnitude greater than that of electronic systems. A recent article shows that the maximum on/off chip communication rate of the CMOS-SEED bitonic sorter built by the Scottish Collaboration Initiative in Optoelectronic Sciences (SCIOS) is 5.2 10¹¹ pin-Hz [3]. This technology, called hybrid or smart-pixel-array technology, has provoked studies of the issues involved in determining the complexity of each processing element (the pixel) in order to optimize the overall system performance [3-5]. In order to contribute to the debate, the purpose of this article is fourfold: (i) to show that such performance relies on a small set of parameters which characterize the processing element in the optical and electronic domains as shown in table 1, (ii) to demonstrate that optimum performance lies in a narrow niche of the resulting parameter space, (iii) to indicate which technology has to be improved in order to harvest the full communication rate of such systems, and (iv) to outline an unexpected application for which the hybrid technology could contribute significantly.

© 1997 Optical Society of America