Abstract

Over the last few years, micron-size opto-electronic devices have become key components in optically interconnected electronic chips. The possibility of integrating these components in conventional electronic families (ECL,CMOS,FET) has allowed the design of various hybrid processing units [1] whose common feature is the optical reception, modulation or emission and the electronic treatment of information. The use of this hybrid technology, defined as smart pixel technology, has provoked recent studies on whether the performance of a smart pixel array [2, 3], its cost and reliability [4, 5] can be regarded as a viable solution in optical information processing. This paper focusses on the current issues involved in increasing the complexity of individual processing nodes in order to optimize the performance of the opto-electronic processor array. The optimum smartness of the pixel, that is, its optimum degree of complexity is quantified on algorithmic, electronic and optical grounds. Having in mind a particular task, such as data sorting, performance metrics of the system are analyzed in terms of its throughtput rate, power consumption, real-estate and laser source power requirements. The use of a particular example, such as the bitonic sorter [6], allows us to quantify exactly the power dissipated and the layout area occupied by the smart pixel in each of the different electronic families examined. Finally optically-induced electronic power dissipation necessitates to decrease the optical power at each photodetector for a given operating frequency and bit-error rate (BER). This issue is analysed in the context of global optimization of the emitter (or modulator) and detector associated with each pixel.

© 1995 Optical Society of America