3.2Tb/s Heterogeneous Photonic Integrated Circuit Chip in a Co-Packaged Optics Configuration

Damien Lambert; Jeff Rahn; Majid Sodagar; Murtaza Askari; Paveen Apiratikul; John Spann; Thang Pham; Yishen Huang; Stephen Krasulick

doi:10.1364/OFC.2023.W3D.2

Abstract

We present a low-cost, scalable 3.2Tbps heterogenous photonic integrated circuit chip assembled in a co-packaged optics configuration. The integration of III-V material directly into the Silicon-Photonic chip offers clear form-factor, density, and thermal dissipation advantages.

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