Abstract

As semiconductor and electronic technologies approach fundamental physical limits in scaling and performance, the trend in high-performance computer design is to use large-scale to massively parallel architectures [1, 2, 3]. While the technology to design high-speed processing elements (PEs) has progressed significantly, the progress on designing high-performance interconnection network has not been adequate. Unfortunately, the bottleneck in performance of massively parallel architectures is typically the limited bandwidth of current interconnection networks. This is because while PEs can be densely packed on a printed wire board (PWB), there is never enough space on the board to provide all interconnection channels required for inter-PE communication at the maximum possible bandwidth. As a result, each PE is usually destined to communicate serially, often sharing communication channels with other PEs (e.g., 16 PEs in the Connection Machine share one serial line). This problem is particularly critical in fine-grained architectures where the processing time in relatively simple PEs is comparable to the communication overhead between PEs.

© 1989 Optical Society of America