Abstract

This paper will discuss the realized and projected picosecond logic speed of Resistor Coupled Josephson Logic for LSI applications. The 4b x 4b parallel multiplier, developed very recently by using 5-μm lead alloy technology, demonstrates a multiplication time as small as 280 picoseconds. The averaged logic delay per gate is 21 picoseconds in this multiplier. The advancement in Josephson IC fabrication technology, on the other hand, has shown the possibility for fabricating 1-μm minimum line width Josephson LSI. The projested logic delay per gate of densely packed 1-μm RCJL LSI will be less than 10 picoseconds.

© 1985 Optical Society of America