Abstract

Search for high speed has over the years focussed on miniturization and high performance semiconducting materials. Scaling up in speed reaches a saturation as the dimensions are reduced because parasitics do not entirely scale down, particularly in integrated circuits. As a result new material systems e.g. GaAs/AlGaAs modulation doped structures with enhanced transport properties have received a great deal of attention. The propagation delay in Si devices (both bipolars and FETs) appear to have reached a limit at around 30 ps while the bulk GaAs FETs operate around 15 ps. Near 10 ps and sub 10 ps switching speeds however belong to modulation doped GaAs/AlGaAs FETs with ~ 0.5μ gate lengths. Hetero junction GaAs/AlGaAs bipolar transistors are expected to reach the 10ps range in a few years being at ~30 ps at the present time. It is becoming very clear that the progress below 10 ps in a given material system is very difficult because of parasitics. The 10 ps switchings time obtained for an individual device (gate) can not be maintained in a real circuit where a chain of gates are used, again because of parasitics and interconnects causing delays. If it were not for the delays associated with the input capacitance changing time and other parasitic effects, intrinsic delays of about 1 ps should be possible. In field effect transistors for example, it is fair to assume that a great portion of the delay arises from input and output charging times. Obviously lowering the lateral dimension (e.g. gate) alone does not necessarily lead to expected improvements in speed. This is even more so in heterojunction bipolar transistors where the input charging time accounts for about 75% of the total delay time: therefore, reducing the base width further, well under 0.1μm may not necessarily lead to faster operation.

© 1985 Optical Society of America