Abstract

The design and fabrication of optoelectronic arrays poses a new set of problems not encountered with individual devices. These include smaller feature size, tighter tolerances, a bus structure, planarization and step coverage issues. The later two issues are particularly problematic with vertically integrated devices, such as the LAOS, since the mesas are greater than 3 μm high. This paper discusses these design/fabrication issues and illustrates some solutions.

© 1993 Optical Society of America