Abstract
In future optical packet switching nodes, many kinds of processing functions for high-speed asynchronous burst optical packets such as address recognition, buffering, bit-rate conversion, and 3R regeneration may be needed. However, an increase in the optical packet bit rate will increase the difficulty in using electronics circuits. To overcome the difficulty in address recognition, several approaches to label coding such as a sub-carrier or a slow wavelength label have been demonstrated. On the other hand, we have previously proposed a novel self-serial-to-parallel conversion (self-SPC) scheme1 with a single optical clock pulse generator2 for label recognition of a burst high-speed optical packet, and demonstrated 400-Gb/s, 6-bit SPC. In self-SPC, all bits of the incoming serial label are automatically converted to parallel bits using the single optical pulse generated based on the first bit of the label. This makes label recognition using CMOS electronic circuits easy. An attractive way to solve the remaining problems -buffering, bit-rate conversion, 3R regeneration, and head of line (HOL) blocking- is to develop a photonic random access memory (RAM) that can process the high-speed burst optical packets. In the photonic RAM, silicon electronics memory devices would be sandwiched by an all-optical SP converter and electrical parallel-to-optical serial converter, and the input and the output packets would be in the optical domain. Such high-speed photonic RAM will need a compact SP converter module with so many parallel outputs (100-ch) that the high-speed optical packets (both label and payload) can be converted parallel to the operation speed of the silicon electronic memories (less than 1 Gb/s). In this paper, we develop an 18-ch compact SP converter module, and demonstrate 1-Tb/s 16-bit all-optical SPC with an ultrafast surface-reflection all-optical switch made of low-temperature-grown Be-doped strained In-GaAs/InAlAs MQWs.
© 2002 Optical Society of America
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