Abstract

Results are being presented from a work aimed at demonstrating the feasibility of silicon FET technology in the 0.1μm gate length regime. Self-aligned, n-channel polysilicon gated MOSFETs were designed for operation at 77°K, with reduced power-supply levels. Noteworthy results of the exercise were: observing clear manifestation of velocity overshoot which resulted in extrinsic transconductance of over 940μS/μm at 0.07μm gate-length, measuring 13ps delay per stage in 0.1 μm gate length ring oscillators, with simulations showing potential for below 5ps performance.

© 1989 Optical Society of America