Abstract

The total overlay budget in semiconductor lithography has many components, including mask dimensional accuracy, tool-to-tool printing distortion, and process bias, but historically alignment registration has been the most critical. Yet progress in alignment has not kept pace with the exponential increases in printing resolution achieved during the last 10 years. In manufacturing, it is difficult to overlay lithography levels better than 200 nm at the 3 σ confidence level. Registration accuracy is limited by the complex interaction of the alignment optics with wafer registration marks at different process levels. Recent experimental and analytical work has led to an understanding of how to design optical alignment systems with reduced sensitivity to mark structure, coatings and processing. However, it is possible that no single alignment system can be optimized .for all process layers encountered in the fabrication of DRAMS or bipolar logic.

© 1991 Optical Society of America