Expand this Topic clickable element to expand a topic
Skip to content
Optica Publishing Group

OEIC Architecture for a High Order Correlation Connectionist Network

Not Accessible

Your library or personal account may give you access

Abstract

The extraction of features of two or more consecutive scans from pictures is of great interest in today’s world. The technique of high order correlation to track dim targets has been developed at Colorado State University to accomplish this task.1 We have designed and had fabricated an optoelectronic chip (OEIC) though the MIT OPTOCHIP program as a first demonstration of this neural network. The chips have the ability to perform hard limit thresholding, store the outputs, and broadcast the outputs to the next stage. This paper will discuss the high order correlation neural network, and the optoelectronic chips designed as a demonstrator for the network.

© 1997 Optical Society of America

PDF Article
More Like This
Smart Pixel Array Network Interface (SAPIENT) for 2D Parallel Data Packet Networks

C.-H. Chen, B. Hoanca, C.B. Kuznia, J.-M. Wu, and A.A. Sawchuk
OThD.11 Optics in Computing (IP) 1997

Smart-Pixel Implementation of Network Router Deadlock Handling Mechanisms

Timothy Mark Pinkston, Mongkol Raksapatcharawong, and Yungho Choi
OThB.2 Optics in Computing (IP) 1997

GaAs Smart Pixel Arrays for High Performance Optoelectronic Computing Modules

D. S. McCallum, J. W. Kim, P. S. Guilfoyle, W. H. Chang, J. Mu, and M. Feng
OFB.3 Optics in Computing (IP) 1997

Select as filters


Select Topics Cancel
© Copyright 2024 | Optica Publishing Group. All rights reserved, including rights for text and data mining and training of artificial technologies or similar technologies.